UPSD3422 datasheet(125/293 Pages) STMICROELECTRONICS

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uPSD34xx

I2C interface

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23.12

I2C START sample setting (S1SETUP)

The S1SETUP register (Table 59) determines how many times an I2C bus START condition

will be sampled before the SIOE validates the START condition, giving the SIOE the ability

to reject noise or illegal transmissions.

Because the minimum duration of an START condition varies with I2C bus speed (fSCL), and

also because the uPSD34xx may be operated with a wide variety of frequencies (fOSC), it is

necessary to scale the number of samples per START condition based on fOSC and fSCL.

In Slave mode, the SIOE recognizes the beginning of a START condition when it detects a

'1'-to-'0' transition on the SDA bus line while the SCL line is high (see Figure 42 on

page 117). The SIOE must then validate the START condition by sampling the bus lines to

ensure SDA remains low and SCL remains high for a minimum amount of hold time,

tHLDSTA. Once validated, the SIOE begins receiving the address byte that follows the START

condition.

If the EN_SS Bit (in the S1SETUP Register) is not set, then the SIOE will sample only once

after detecting the '1'-to-'0' transition on SDA. This single sample is taken 1/fOSC seconds

after the initial 1-to-0 transition was detected. However, more samples should be taken to

ensure there is a valid START condition.

To take more samples, the SIOE should be initialized such that the EN_SS Bit is set, and a

value is written to the SMPL_SET[6:0] field of the S1SETUP Register to specify how many

samples to take. The goal is to take a good number of samples during the minimum START

condition hold time, tHLDSTA, but no so many samples that the bus will be sampled after

tHLDSTA expires.

Table 60 on page 126 describes the relationship between the contents of S1SETUP and the

resulting number of I2C bus samples that SIOE will take after detecting the 1-to-0 transition

on SDA of a START condition.

Important note: Keep in mind that the time between samples is always 1/fOSC.

The minimum START condition hold time, tHLDSTA, is different for the three common I

speed categories per Table 61 on page 126.

Table 59.

S1SETUP: I2C START condition sample setup register (SFR DBh, reset

value 00h)

Note:

Sampling SCL and SDA lines begins after '1'-to-'0' transition on SDA occurred while SCL is

high. Time between samples is 1/fOSC.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EN_SS

SMPL_SET[6:0]

Bit

Symbol

R/W

Function

7EN_SS

R/W

Enable Sample Setup

EN_SS = 1 will force the SIOE to sample(1) a START condition

on the bus the number of times specified in SMPL_SET[6:0].

EN_SS = 0 means the SIOE will sample(1) a START condition

only one time, regardless of the contents of SMPL_SET[6:0].

6:0

SMPL_SET

[6:0]

–

Sample Setting

Specifies the number of bus samples(1) taken during a START

condition. See Table 60 for values.

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