UPSD3422 datasheet(151/293 Pages) STMICROELECTRONICS

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uPSD34xx

USB interface

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Figure 54.

FIFOs with no Pairing

●

Pairing FIFOs Example

Now assume that IN Endpoint1 and Endpoint2 FIFOs are paired for double buffering

and the same 1024 bytes of data are to be transferred to the host. As in the non-

pairing example, the CPU loads the IN Endpoint0 FIFO with 64 bytes of data. Instead

of having to wait for the SIE to transfer the 64 bytes of data to the host, the CPU can

write another 64 bytes of data to IN Endpoint0 FIFO. While the CPU is writing the

second packet of 64 bytes of data into the FIFO, the SIE is sending the first packet of

64 bytes of data to the host. After the CPU has written the second packet of 64 bytes to

the FIFO, it waits a shorter amount of time for the SIE to complete sending the first

packet of data since they were working concurrently. As soon as the first packet is sent

by the SIE, the second packet is immediately available to be sent by the SIE since the

FIFO was already loaded by the MCU. Also, after the first packet is sent by the SIE, the

alternate FIFO is available for the MCU to load the third packet of 64 bytes of data.

With double buffering, the MCU is able to always have a FIFO loaded and ready with

data to be sent by the SIE when the host sends an IN token maximizing the data

transfer rate.

8032

MCU

USB SFRs

Serial

Interface

Engine

CTRL

XDATA

AI10493

Endpoint4 IN FIFO

Endpoint3 IN FIFO

Endpoint2 IN FIFO

Endpoint1 IN FIFO

Endpoint0 IN FIFO

Endpoint0 OUT FIFO

Endpoint1 OUT FIFO

Endpoint2 OUT FIFO

Endpoint3 OUT FIFO

Endpoint4 OUT FIFO

FIFO

Interface

Logic

Endpoint4

Endpoint3

Endpoint2

Endpoint1

Endpoint0

Endpoint1

Endpoint2

Endpoint3

Endpoint4

UPSD3422 Datasheet(PDF) 151 Page - STMicroelectronics

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