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UPSD3422 Datasheet(PDF) 162 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 162 Page - STMicroelectronics |
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162 / 293 page  USB interface uPSD34xx 162/293 ● USB IN FIFO NAK Interrupt Flag (UIF3) The USB IN FIFO NAK Interrupt Flag register (see Table 79) contains flags that indicate when an IN Endpoint FIFO is not ready. The Endpoint FIFO is not ready when data has not been loaded into its FIFO and the USIZE register has not been written to (writing to the USIZE register puts the FIFO in a “ready” to send data state). Until the FIFO is ready, the SIE will continue to NAK all IN requests to the respective Endpoint. Once set, firmware must clear the flag by writing a '0' to the appropriate bit. When FIFOs are paired, only the odd numbered FIFO Interrupt Flags are active. Table 79. USB IN FIFO NAK interrupt flag (UIF3 0EBh, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – NAK4F NAK3F NAK2F NAK1F NAK0F Bit Symbol R/W Definition 7 – – Reserved 6 – – Reserved 5 – – Reserved 4 NAK4F R/W Endpoint 4 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready. 3 NAK3F R/W Endpoint 3 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready. 2 NAK2F R/W Endpoint 2 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready. 1 NAK1F R/W Endpoint 1 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready. 0 NAK0F R/W Endpoint 0 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready. |
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