UPSD3422 datasheet(212/293 Pages) STMICROELECTRONICS

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PSD module

uPSD34xx

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28.5.22

Flash memory protection during power-up

Flash memory WRITE operations are automatically prevented while VDD is ramping up until

it rises above VLKO voltage threshold at which time Flash memory WRITE operations are

allowed.

28.5.23

PSD module security bit

A programmable security bit in the PSD Module protects its contents from unauthorized

viewing and copying. The security bit is set using PSDsoft Express and programmed into

the PSD Module with JTAG. When set, the security bit will block access of JTAG

programming equipment from reading or modifying the PSD Module Flash memory and

PLD configuration. The security bit also blocks JTAG access to the MCU Module for

debugging. The only way to defeat the security bit is to erase the entire PSD Module using

JTAG (erase is the only JTAG operation allowed while security bit is set), after which the

device is blank and may be used again. The 8032 MCU will always have access to Flash

memory contents through its 8-bit data bus even while the security bit is set. The 8032 can

read the status of the security bit at run-time (but it cannot change it) by reading the csiop

Table 109.

Main Flash memory protection register definition (address = csiop +

offset C0h)

Note:

Bit Definitions:

Sec_Prot 1 = Flash memory sector is write protected, 0 = Flash memory sector is

not write protected.

Table 110.

Secondary Flash memory protection/security register definition (csiop +

offset C2h)

Note:

Security_Bit = 1, device is secured, 0 = not secured

Note:

Sec_Prot 1 = Flash memory sector is write protected, 0 = Flash memory sector is

not write protected.

28.5.24

PLDs

The PSD Module contains two PLDs: the Decode PLD (DPLD), and the General PLD

(GPLD), as shown in Figure 74 on page 215. Both PLDs are fed by a common PLD input

signal bus, and additionally, the GPLD is connected to the 8032 data bus.

PLD logic is specified using PSDsoft Express and programmed into the PSD Module using

the JTAG ISP channel. PLD logic is non-volatile and available at power-up. PLDs may not be

programmed by the 8032. The PLDs have selectable levels of performance and power

consumption.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sec7_Prot

Sec6_Prot

Sec5_Prot

Sec4_Prot

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Security_Bit

not used

Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

UPSD3422 Datasheet(PDF) 212 Page - STMicroelectronics

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