UPSD3422 datasheet(209/293 Pages) STMICROELECTRONICS

209 / 293 page

uPSD34xx

PSD module

209/293

indicate when an erase or program operation is complete (requires routing the signal on PC

board from PC3 back into a pin on the MCU Module). This signal is also available internally

on the PSD Module as an input to both PLDs (without routing a signal externally on PC

board) and its signal name is “rd_bsy”. The Ready/Busy output can be probed during lab

development to check the timing of Flash memory programming in the system at run-time.

28.5.13

Bypassed unlock sequence

The Bypass Unlock mode allows the 8032 to program bytes in the Flash memories faster

than using the standard Flash program instruction sequences because the typical AAh, 55h

unlock bus cycles are bypassed for each byte that is programmed. Bypassing the unlock

sequence is typically used when the 8032 is intentionally programming a large number of

bytes (such as during IAP). After intentional programming is complete, typically the Bypass

mode would be disabled, and full protection is back in place to prevent unwanted WRITEs to

Flash memory.

The Bypass Unlock mode is entered by first initiating two Unlock bus cycles. This is followed

by a third WRITE operation containing the Bypass Unlock command, 20h (as shown in

Table 107 on page 203). The Flash memory array that received that sequence then enters

the Bypass Unlock mode. After this, a two bus cycle program operation is all that is required

to program a byte in this mode. The first bus cycle in this shortened program instruction

sequence contains the Bypassed Unlocked Program command, A0h, to any valid address

within the unlocked Flash array. The second bus cycle contains the address and data of the

byte to be programmed. Programming status is checked using toggle, polling, or

Ready/Busy just as before. Additional data bytes are programmed the same way until this

Bypass Unlock mode is exited.

To exit Bypass Unlock mode, the system must issue the Reset Bypass Unlock instruction

sequence. The first bus cycle of this instruction must write 90h to any valid address within

the unlocked Flash Array; the second bus cycle must write 00h to any valid address within

the unlocked Flash Array. After this sequence the Flash returns to Read Array mode.

During Bypass Unlock Mode, only the Bypassed Unlock Program instruction, or the Reset

Bypass Unlock instruction is valid, other instruction will be ignored.

28.5.14

Erasing Flash memory

Flash memory may be erased sector-by-sector, or an entire Flash memory array may be

erased with one command (bulk).

28.5.15

Flash bulk erase

The Flash Bulk Erase instruction sequence uses six WRITE operations followed by a READ

operation of the status register, as described in Table 107 on page 203. If any byte of the

Bulk Erase instruction sequence is wrong, the Bulk Erase instruction sequence aborts and

the device is reset to the Read Array mode. The address provided by the 8032 during the

Flash Bulk Erase command sequence may select any one of the eight Flash memory sector

select signals FSx or one of the four signals CSBOOTx. An erase of the entire Flash

memory array will occur in a particular array even though a command was sent to just one of

the individual Flash memory sectors within that array.

During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit

(DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7). The Error Flag Bit

(DQ5) returns a ’1’ if there has been an erase failure. Details of acquiring the status of the

UPSD3422 Datasheet(PDF) 209 Page - STMicroelectronics

UPSD3422 Datasheet(HTML) 209 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL