UPSD3422 datasheet(207/293 Pages) STMICROELECTRONICS

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uPSD34xx

PSD module

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attempted to program bit to logic ’1’ when that bit was already programmed to logic ’0’ (must

erase to achieve logic ’1’).

It is suggested (as with all Flash memories) to read the location again after the embedded

programming algorithm has completed, to compare the byte that was written to the Flash

memory with the byte that was intended to be written.

When using the Data Polling method during an erase operation, Figure 72 still applies.

However, the Data Polling Flag Bit (DQ7) is '0' until the erase operation is complete. A ’1’ on

the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle, a ’0’ indicates no

error. The 8032 can read any location within the sector being erased to get the Data Polling

Flag Bit (DQ7) and the Error Flag Bit (DQ5).

Figure 72.

Data polling flowchart

28.5.11

Data Toggle

Checking the Toggle Flag Bit (DQ6) is another method of determining whether a program or

erase operation is in progress or has completed. Figure 73 shows the Data Toggle

algorithm.

When the 8032 issues a program instruction sequence, the embedded algorithm within the

Flash memory array begins. The 8032 then reads the location of the byte to be programmed

in Flash memory to check status. The Toggle Flag Bit (DQ6) of this location toggles each

time the 8032 reads this location until the embedded algorithm is complete. The 8032

continues to read this location, checking the Toggle Flag Bit (DQ6) and monitoring the Error

Flag Bit (DQ5). When the Toggle Flag Bit (DQ6) stops toggling (two consecutive reads yield

the same value), then the embedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,'

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

FAIL

PASS

AI01369B

DQ7

DATA

YES

DQ5

= 1

DQ7

DATA

YES

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