UPSD3422 datasheet(244/293 Pages) STMICROELECTRONICS

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PSD module

uPSD34xx

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Table 145.

Power management mode register PMMR2 (address = csiop + offset B4h)

Note:

The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST)

pulses do not clear the registers.

Note:

Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD

logic equation.

Table 146.

Power Management Mode Register PMMR3 (address = csiop + offset C7h)

Note:

The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST)

pulses do not clear the registers.

Bit 0

Not used, and should be set to zero.

Bit 1

Not used, and should be set to zero.

Bit 2

Blocking Bit,

WR to

PLDs(1)

0 =

8032 WR input to the PLD Input Bus is not blocked.

1 =

off

8032 WR input to PLD Input Bus is blocked, saving power.

Bit 3

Blocking Bit,

RD to

PLDs(1)

0 =

8032 RD input to the PLD Input Bus is not blocked.

1 =

off

8032 RD input to PLD Input Bus is blocked, saving power.

Bit 4

Blocking Bit,

PSEN to

PLDs(1)

0 =

8032 PSEN input to the PLD Input Bus is not blocked.

1 =

off

8032 PSEN input to PLD Input Bus is blocked, saving power.

Bit 5

Blocking Bit,

ALE to

PLDs(1)

0 =

8032 ALE input to the PLD Input Bus is not blocked.

1 =

off

8032 ALE input to PLD Input Bus is blocked, saving power.

Bit 5

Blocking Bit,

PC7 to

PLDs(1)

0 =

Pin PC7 input to the PLD Input Bus is not blocked.

1 =

off

Pin PC7 input to PLD Input Bus is blocked, saving power.

Bit 7

Not used, and should be set to zero.

Bit 0

Not used, and should be set to zero.

Bit 1

FORCE_PD

0 =

off

APD counter will cause Power-Down Mode if APD is enabled.

1 =

Power-Down mode will be entered immediately regardless of APD

activity.

Bit 3-

Not used, and should be set to zero.

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