UPSD3422 datasheet(241/293 Pages) STMICROELECTRONICS

241 / 293 page

uPSD34xx

PSD module

241/293

Figure 88.

Port D structure

Note:

Optional function on a specific Port D pin.

28.5.51

Power management

The PSD Module offers configurable power saving options, and also a way to manage

power to the SRAM (battery backup). These options may be used individually or in

combinations. A top level description for these functions is given here, then more detailed

descriptions will follow.

●

Zero-Power Memory: All memory arrays (Flash and SRAM) in the PSD Module are

built with zero-power technology, which puts the memories into standby mode (~ zero

DC current) when 8032 address signals are not changing. As soon as a transition

occurs on any address input, the affected memory “wakes up”, changes and latches its

outputs, then goes back to standby. The designer does not have to do anything special

I/O PORT D

LOGIC

DIRECTION

DRIVE SELECT

DATA OUT

(MCUI/O)

ENABLE OUT

DATA IN (MCUI/O)

PT OUTPUT ENABLE (.OE)

OUTPUT

ENABLE

OUTPUT

ENABLE

TYPICAL

PIN, PORT D

PSD MODULE RESET

ONE of 5

CSIOP

REGISTERS

FROM DPLD EXTERNAL CHIP (ECSx)

FROM PLD

INPUT BUS

FROM AND-

OR ARRAY

FROM DPLD

CLR

DIRECTION

DRIVE

(MCUI/O)

DATA OUT

8032

RESET

PSDsoft

8032 RD

TO POWER MANAGEMENT AND PLD INPUT BUS

CSIOP

REGIS-

TERS

DRIVE TYPE SELECT

8032

DATA

BITS

8032

DATA

BIT

PIN INPUT

CMOS

BUFFER

HYSTERESIS

VDD

OUTPUT

1 = FAST

SLEW RATE

PD1. PIN, PD2.PIN

DIRECTLY TO PLD INPUT BUS, NO IMC

CSI

(1)

TO POWER MANAGEMENT

CLKIN

(1)

AI09182

UPSD3422 Datasheet(PDF) 241 Page - STMicroelectronics

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