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UPSD3422 Datasheet(PDF) 239 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 239 Page - STMicroelectronics |
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239 / 293 page ![]() uPSD34xx PSD module 239/293 if they are used for 6-pin JTAG. See Section 28.6.1: JTAG ISP and JTAG debug on page 251 for details. – PC2 can be used as a voltage input (from battery or other DC source) to backup the contents of SRAM when VDD is lost. This function is specified in PSDsoft Express as Section 28.5.62: SRAM standby mode (battery backup) on page 250. – PC3 can be used as an output to indicate when a Flash memory program or erase operation has completed. This is specified in PSDsoft Express as Section 28.5.12: Ready/Busy (PC3) on page 208. – PC4 can be used as an output to indicate when the SRAM has switched to backup voltage (when VDD is less than the battery input voltage on PC2). This is specified in PSDsoft Express as “Standby-On Indicator” (see Section 28.5.62: SRAM standby mode (battery backup) on page 250). The remaining four pins (TDI, TDO, TCK, TMS) on Port C are dedicated to the JTAG function and cannot be used for any other function. See Section 28.6.1: JTAG ISP and JTAG debug on page 251. Port C also supports the Open Drain output drive type options on pins PC2, PC3, PC4, and PC7 using the csiop Drive Select registers. Figure 87. Port C structure Note: 1 Pull-up switches to VBAT when SRAM goes to battery back-up mode. 2 Optional function on a specific Port C pin. I/O PORT C LOGIC O U T P U T M U X P D B M U X DIRECTION DRIVE SELECT DATA OUT (MCUI/O) ENABLE OUT DATA IN (MCUI/O) PT OUTPUT ENABLE, .OE (JTAG STATE MACHINE AUTOMATICALLY CONTROLS OE FOR JTAG SIGNALS) OUTPUT ENABLE TYPICAL PIN, PORT C PSD MODULE RESET ONE of 6 CSIOP REGISTERS 1 2 3 4 5 1 2 3 4 5 FROM OMC OUTPUT (MCELLBCx) STANDBY ON (2) FROM SRAM BACK-UP CIRCUIT FROM FLASH MEMORIES TO/FROM JTAG STATE MACHINE FROM PLD INPUT BUS FROM AND- OR ARRAY FROM OMC ALLOCATOR D CLR DIRECTION DRIVE (MCUI/O) DATA OUT 8032 WR RESET PSDsoft 8032 RD TO IMCs CSIOP REGIS- TERS Q Q Q DRIVE TYPE SELECT (2) 8032 DATA BITS 8032 DATA BIT PIN INPUT CMOS BUFFER NO HYSTERESIS VDD VDD/VBAT (1) VDD/VBAT (1) PIN OUTPUT 50k PULL-UP ONLY ON JTAG TDI, TMS, TCK SIGNALS TO SRAM BATTERY BACK-UP CIRCUIT (2) IMCC2, IMCC3, IMCC4, IMCC7 RDY/BSY (2) TDO, TSTAT (2), TERR(2) TDI, TMS, TCK AI09181 |
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