UPSD3422 datasheet(236/293 Pages) STMICROELECTRONICS

236 / 293 page

PSD module

uPSD34xx

236/293

Table 140.

Port A enable out register(1) (address = csiop + offset 0Ch)

Note:

Port A not available on 52-pin uPSD34xx devices

For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin

used as input)

Table 141.

Port B enable out register (address = csiop + offset 0Dh)

Note:

For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin

used as input)

Table 142.

Port C enable out register (address = csiop + offset 1Ah)

Note:

For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin

used as input)

Table 143.

Port D enable out register (address = csiop + offset 1Bh)

Note:

For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin

used as input)

Pin is not available on 52-pin uPSD34xx devices

28.5.46

Individual port structures

Ports A, B, C, and D have some differences. The structure of each individual port is

described in the next sections.

28.5.47

Port A structure

Port A supports the following operating modes:

●

MCU I/O Mode

●

GPLD Output Mode from Output Macrocells MCELLABx

●

GPLD Input Mode to Input Macrocells IMCAx

●

Latched Address Output Mode

●

Peripheral I/O Mode

Port A also supports Open Drain/Slew Rate output drive type options using csiop Drive

Select registers. Pins PA0-PA3 can be configured to fast slew rate, pins PA4-PA7 can be

configured to Open Drain Mode.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PA7 OE

PA6 OE

PA5 OE

PA4 OE

PA3 OE

PA2 OE

PA1 OE

PA0 OE

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PB7 OE

PB6 OE

PB5 OE

PB4 OE

PB3 OE

PB2 OE

PB1 OE

PB0 OE

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PC7 OE

N/A

(JTAG)

N/A

(JTAG)

PC4 OE

PC3 OE

PC2 OE

N/A

(JTAG)

N/A

(JTAG)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

PD2 OE(2)

PD1 OE

N/A

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