UPSD3422 datasheet(234/293 Pages) STMICROELECTRONICS

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PSD module

uPSD34xx

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28.5.41

JTAG ISP mode

Four of the pins on Port C are based on the IEEE 1149.1 JTAG specification and are used

for In-System Programming (ISP) of the PSD Module and debugging of the 8032 MCU

Module. These pins (TDI, TDO, TMS, TCK) are dedicated to JTAG and cannot be used for

any other I/O function. There are two optional pins on Port C (TSTAT and TERR) that can be

used to reduce programming time during ISP. See Section 28.6.1: JTAG ISP and JTAG

debug on page 251.

28.5.42

Other port capabilities

It is possible to change the type of output drive on the ports at run-time. It is also possible to

read the state of the output enable signal of the output driver at run-time. The following

sections provide the details.

28.5.43

Port pin drive options

The csiop Drive Select registers allow reconfiguration of the output drive type for certain

pins on Ports A, B, C, and D. The 8032 can change the default drive type setting at run-time.

The is no action needed in PSDsoft Express to change or define these pin output drive

types. Figure 80 on page 226 shows the csiop Drive Select register output controlling the

pin output driver. The default setting for drive type for all pins on Ports A, B, C, and D is a

standard CMOS push-pull output driver.

Note:

When a pin on Port A, B, C, D is not used as an output and has no external device driving it

as an input (floating pin), excess power consumption can be avoided by placing a weak pull-

up resistor (100K

Ω) to V

DD which keeps the CMOS input pin from floating.

28.5.44

Drive select registers

The csiop Drive Select Registers will configure a pin output driver as Open Drain or CMOS

push/pull for some port pins, and controls the slew rate for other port pins. An external pull-

up resistor should be used for pins configured as Open Drain, and the resistor should be

sized not to exceed the current sink capability of the pin (see DC specifications). Open Drain

outputs are diode clamped, thus the maximum voltage on an pin configured as Open Drain

is VDD + 0.7V.

A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is

set to logic '1.'

Note:

The slew rate is a measurement of the rise and fall times of an output. A higher slew rate

means a faster output response and may create more electrical noise. A pin operates in a

high slew rate when the corresponding bit in the Drive Register is set to '1.' The default rate

is standard slew rate (see AC specifications).

Table 136 through Table 139 on page 235 show the csiop Drive Registers for Ports A, B, C,

and D. The tables summarize which pins can be configured as Open Drain outputs and

which pins the slew rate can be changed. The default output type is CMOS push/pull output

with normal slew rate.

28.5.45

Enable out registers

The state of the output enable signal for the output driver at each pin on Ports A, B, C, and D

can be read at any time by the 8032 when it reads the csiop Enable Output registers. Logic

'1' means the driver is in output mode, logic ’0’ means the output driver is in high-impedance

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