UPSD3422 datasheet(230/293 Pages) STMICROELECTRONICS

230 / 293 page

PSD module

uPSD34xx

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Table 132.

MCU I/O mode port C direction register (address = csiop + offset 14h)

Note:

For each bit, 1 = out from uPSD34xx port pin1, 0 = in to PSD34xx port pin

Default state for register is 00h after reset or power-up

Table 133.

MCU I/O mode port D direction register (address = csiop + offset 15h)

Note:

For each bit, 1 = out from uPSD34xx port pin1, 0 = in to PSD34xx port pin

Default state for register is 00h after reset or power-up

Not available on 52-pin uPSD34xx devices

28.5.38

PLD I/O mode

Pins on Ports A, B, C, and D can serve as inputs to either the DPLD or the GPLD. Inputs to

these PLDs from Ports A, B, and C are routed through IMCs before reaching the PLD input

bus. Inputs to the PLDs from Port D do not pass through IMCs, but route directly to the PLD

input bus.

Pins on Ports A, B, and C can serve as outputs from GPLD OMCs, and Port D pins can be

outputs from the DPLD (external chip-selects) which do not consume OMCs.

Whenever a pin is specified to be a PLD output, it cannot be used for MCU I/O mode, or

other pin modes. If a pin is specified to be a PLD input, it is still possible to read the pin using

MCU I/O input mode with the csiop register Data In. Also, the csiop Direction register can

still affect a pin which is used for a PLD input. The csiop Data Out register has no effect on a

PLD output pin.

Each pin on Ports A, B, C, and D have a tri-state buffer at the final output stage. The Output

Enable signal for this buffer is driven by the logical OR of two signals. One signal is an

Output Enable signal generated by the AND-OR array (from an .oe equation specified in

PSDsoft), and the other signal is the output of the csiop Direction register. This logic is

shown in Figure 80 on page 226. At power-on, all port pins default to high-impedance input

(Direction registers default to 00h). However, if an equation is written for the Output Enable

that is active at power-on, then the pin will behave as an output.

PLD I/O equations are specified in PSDsoft Express and programmed into the uPSD using

JTAG. Figure 81 shows a very simple combinatorial logic example which is implemented on

pins of Port B.

To give a general idea of how PLD logic is implemented using PSDsoft Express, Figure 82

on page 231 illustrates the pin declaration window of PSDsoft Express, showing the PLD

output at pin PB0 declared as “Combinatorial” in the “PLD Output” section, and a signal

name, “pld_out”, is specified. The other three signals on pins PB1, PB2, and PB3 would be

declared as “Logic or Address” in the “PLD Input” section, and given signal names.

In the “Design Assistant” window of PSDsoft Express shown in Figure 83 on page 232, the

user simply enters the logic equation for the signal “pld_out” as shown. The user can either

type in the logic statements or enter them using a point-and-click method, selecting various

signal names and logic operators available in the window.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PC7

N/A

PC4

PC3

PC2

N/A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

PD2(3)

PD1

N/A

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