UPSD3422 datasheet(227/293 Pages) STMICROELECTRONICS

227 / 293 page

uPSD34xx

PSD module

227/293

Note:

MCELLBC outputs available only on pins PC2, PC3, PC4, and PC7.

JTAG pins (PC0/TMS, PC1/TCK, PC5/TDI, PC6/TDO) are dedicated to JTAG pin functions

(cannot be used for general I/O).

Table 121.

Port Configuration Setting Requirements

Latched Address Output

Yes

Latched address

output mode on

page 232

Peripheral I/O Mode

Yes

Peripheral I/O mode

on page 233

JTAG ISP

Yes(2)

JTAG ISP mode on

page 234

Port Operating Mode

Port A (80-pin

only)

Port B

Port C

Port D

Find it

Port

Operating

Mode

Required Action in

PSDsoft Express to

Configure each Pin

Value that 8032

writes to csiop

Control Register

at run-time

Value that 8032

writes to csiop

Direction

time

Value that 8032

writes to Bit 7

(PIO_EN) of csiop

VM Register at

run-time

MCU I/O

Choose the MCU I/O

function and declare

the pin name

Logic '0' (default)

Logic 1 = Out of

uPSD

Logic 0 = Into

uPSD

N/A

PLD I/O

Choose the PLD

function type, declare

pin name, and specify

logic equation(s)

N/A

Direction register

has no effect on a

pin if pin is driven

from OMC output

N/A

Latched

Address Output

Choose Latched

Address Out function,

declare pin name

Logic '1'

Logic '1' Only

N/A

Peripheral I/O

Choose Peripheral

I/O mode function

and specify address

range in DPLD for

PSELx

N/A

PIO_EN Bit = Logic

(default is '0')

4-PIN JTAG ISP

No action required in

PSDsoft to get 4-pin

JTAG. By default

TDO, TDI, TCK, TMS

are dedicated JTAG

functions.

N/A

6-PIN JTAG ISP

(faster

programming)

Choose JTAG TSTAT

function for pin PC3

and JTAG TERR

function for pin PC4.

N/A

UPSD3422 Datasheet(PDF) 227 Page - STMicroelectronics

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