UPSD3422 datasheet(225/293 Pages) STMICROELECTRONICS

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uPSD34xx

PSD module

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28.5.34

I/O ports

There are four programmable I/O ports on the PSD Module: Port A (80-pin device only), Port

B, Port C, and Port D. Ports A and B are eight bits each, Port C is four bits, and Port D is two

bits for 80-pin devices or 1-bit for 52-pin devices. Each port pin is individually configurable,

thus allowing multiple functions per port. The ports are configured using PSDsoft Express

then programming with JTAG, and also by the 8032 writing to csiop registers at run-time.

Topics discussed in this section are:

●

General Port architecture

●

Port Operating Modes

●

Individual Port Structure

28.5.35

General port architecture

The general architecture for a single I/O Port pin is shown in Figure 80 on page 226. Port

structures for Ports A, B, C, and D differ slightly and are shown in Figure 85 on page 237

though Figure 88 on page 241.

Figure 80 on page 226 shows four csiop registers whose outputs are determined by the

value that the 8032 writes to csiop Direction, Drive, Control, and Data Out. The I/O Port logic

contains an output mux whose mux select signal is determined by PSDsoft Express and the

csiop Control register bits at run-time. Inputs to this output mux include the following:

Data from the csiop Data Out register for MCU I/O output mode (All ports)

Latched de-multiplexed 8032 Address for Address Output mode (Ports A and B only)

Peripheral I/O mode data bit (Port A only)

GPLD OMC output (Ports A, B, and C).

The Port Data Buffer (PDB) provides feedback to the 8032 and allows only one source at a

time to be read when the 8032 reads various csiop registers. There is one PDB for each port

pin enabling the 8032 to read the following on a pin-by-pin basis:

MCU I/O signal direction setting (csiop Direction reg)

Pin drive type setting (csiop Drive Select reg)

Latched Addr Out mode setting (csiop Control reg)

MCU I/O pin output setting (csiop Data Out reg)

Output Enable of pin driver (csiop Enable Out reg)

MCU I/O pin input (csiop Data In reg)

A port pin’s output enable signal is controlled by a two input OR gate whose inputs come

from: a product term of the AND-OR array; the output of the csiop Direction Register. If an

output enable from the AND-OR Array is not defined, and the port pin is not defined as an

OMC output, and if Peripheral I/O mode is not used, then the csiop Direction Register has

sole control of the OE signal.

As shown in Figure 80 on page 226, a physical port pin is connected to the I/O Port logic

and is also separately routed to an IMC, allowing the 8032 to read a port pin by two different

methods (MCU I/O input mode or read the IMC).

28.5.36

Port operating modes

I/O Port logic has several modes of operation. Table 115 on page 223 summarizes which

modes are available on each port. Each of the port operating modes are described in

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