UPSD3422 datasheet(235/293 Pages) STMICROELECTRONICS

235 / 293 page

uPSD34xx

PSD module

235/293

mode, making the pin suitable for input mode (read by the input buffer shown in Figure 80 on

page 226). Figure 80 shows the three sources that can control the pin output enable signal:

a product term from AND-OR array; the csiop Direction register; or the Peripheral I/O Mode

logic (Port A only). The csiop Enable Out registers represent the state of the final output

enable signal for each port pin driver, and are defined in Table 140 on page 236 through

Table 143 on page 236.

Table 136.

Port A pin drive select register(1) (address = csiop + offset 08h)

Note:

Port A not available on 52-pin uPSD34xx devices

For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS

push/pull

Default state for register is 00h after reset or power-up

Table 137.

Port B pin drive select register (address = csiop + offset 09h)

Note:

For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS

push/pull

Default state for register is 00h after reset or power-up

Table 138.

Port C pin drive select register (address = csiop + offset 16h)

Note:

For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS

push/pull

Default state for register is 00h after reset or power-up

Table 139.

Port D pin drive select register (address = csiop + offset 17h)

Note:

For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS

push/pull

Default state for register is 00h after reset or power-up

Pin is not available on 52-pin uPSD34xx devices

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PA7

Open Drain

PA6

Open Drain

PA5

Open Drain

PA4

Open Drain

PA3

Slew Rate

PA2

Slew Rate

PA1

Slew Rate

PA0

Slew Rate

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PB7

Open Drain

PB6

Open Drain

PB5

Open Drain

PB4

Open Drain

PB3

Slew Rate

PB2

Slew Rate

PB1

Slew Rate

PB0

Slew Rate

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PC7

Open Drain

N/A (JTAG)

PC4

Open Drain

PC3

Open Drain

PC2

Open Drain

N/A (JTAG)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

PD2(3)

Slew Rate

PD1

Slew Rate

N/A

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