UPSD3422 datasheet(237/293 Pages) STMICROELECTRONICS

237 / 293 page

uPSD34xx

PSD module

237/293

See Figure 85 for details.

Figure 85.

Port A structure

Note:

Port pins PA0-PA3 are capable of Fast Slew Rate output drive option. Port pins PA4-PA7 are

capable of Open Drain output option.

28.5.48

Port B structure

Port B supports the following operating modes:

●

MCU I/O Mode

●

GPLD Output Mode from Output Macrocells MCELLABx, or MCELLBCx (OMC

allocator routes these signals)

●

GPLD Input Mode to Input Macrocells IMCBx

●

Latched Address Output Mode

Port B also supports Open Drain/Slew Rate output drive type options using the csiop Drive

Select registers. Pins PB0-PB3 can be configured to fast slew rate, pins PB4-PB7 can be

configured to Open Drain Mode.

See Figure 86 for detail.

I/O PORT A

LOGIC

DIRECTION

DRIVE SELECT

CONTROL

DATA OUT

(MCUI/O)

ENABLE OUT

DATA IN (MCUI/O)

D BIT, PERIPH I/O MODE

PT OUTPUT ENABLE (.OE)

LATCHED ADDR BIT

MUX

OUTPUT

ENABLE

TYPICAL

PIN, PORT A

PSD MODULE RESET

ONE of 6

CSIOP

REGISTERS

OUTPUT

SELECT

PERIPHERAL I/O

MODE SETS

DIRECTION

FROM OMC OUTPUT (MCELLABx)

FROM PLD

INPUT BUS

FROM AND-

OR ARRAY

FROM OMC

ALLOCATOR

CLR

DIRECTION

DRIVE

CONTROL

(MCUI/O)

DATA OUT

8032

RESET

PSDsoft

8032 RD

PSELx

PERIPH I/O

DATA BIT

TO IMCs

PIO EN

CSIOP

REGIS-

TERS

DRIVE TYPE SELECT

(1)

8032

DATA

BITS

8032

DATA

BIT

PIN INPUT

CMOS

BUFFER

HYSTERESIS

VDD

OUTPUT

1 = OPEN

DRAIN,

PA4 - PA7

1 = FAST

SLEW RATE,

PA0 - PA3

IMCA0 - IMCA7

AI09179

UPSD3422 Datasheet(PDF) 237 Page - STMicroelectronics

UPSD3422 Datasheet(HTML) 237 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL