UPSD3422 datasheet(250/293 Pages) STMICROELECTRONICS

250 / 293 page

PSD module

uPSD34xx

250/293

specified as “Common Clock Input, CLKIN” before programming the device with JTAG to get

the CLKIN function.

Bit 4 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the PLD input bus, but

CLKIN will still reach the APD counter.

Bit 5 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the OMC flip-flops only,

but CLKIN is still available to the PLD input bus and the APD counter.

See Table 144 on page 243 for details.

28.5.62

SRAM standby mode (battery backup)

The SRAM on the PSD Module may optionally be backed up by an external battery (or other

DC source) to make its contents non-volatile. This is achieved by connecting a battery to pin

PC2 on Port C and selecting the “SRAM Standby” function for pin PC2 within PSDsoft

Express. Automatic voltage supply cross-over circuitry is built into the PSD Module to switch

SRAM supply to battery as soon as VDD drops below the voltage level of the battery. SRAM

contents are protected while battery voltage is greater than 2.0V. Pin PC4 on Port C can be

used as an output to indicate that a battery switch-over has occurred. This is configured in

PSDsoft Express by selecting the “Standby On Indicator” option for pin PC4.

28.6

PSD module reset conditions

The PSD Module receives a reset signal from the MCU Module. This reset signal is referred

to as the “RST” input in PSD Module documentation, and it is active-low when asserted. The

character of the RST signal generated from the MCU Module is described in Section 19:

Supervisory functions on page 83.

Upon power-up, and while RST is asserted, the PSD Module immediately loads its

configuration from non-volatile bits to configure the PLDs and other items. PLD logic is

operational and ready for use well before RST is de-asserted. The state of PLD outputs are

determined by equations specified in PSDsoft Express.

The Flash memories are reset to Read Array mode after any assertion of RST (even if a

program or erase operation is occurring).

Flash memory WRITE operations are automatically prevented while VDD is ramping up until

it rises above the VLKO voltage threshold at which time Flash memory WRITE operations

are allowed.

Once the uPSD34xx is up and running, any subsequent reset operation is referred to as a

warm reset, until power is turned off again. Some PSD Module functions are reset in

different ways depending if the reset condition was caused from a power-up reset or a warm

reset. Table 148 on page 251 summarizes how PSD Module functions are affected by

power-up and warm resets, as well as the affect of PSD Module power-down mode (from

APD).

The I/O pins of PSD Module Ports A, B, C, and D do not have weak internal pull-ups.

In MCU I/O mode, Latched Address Out mode, and Peripheral I/O mode, the pins of Ports

A, B, C, and D become standard CMOS inputs during a reset condition. If no external

devices are driving these pins during reset, then these inputs may float and draw excessive

current. If low power consumption is critical during reset, then these floating inputs should

be pulled up externally to VDD with a weak (100KΩ minimum) resistor.

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