UPSD3422 datasheet(252/293 Pages) STMICROELECTRONICS

252 / 293 page

PSD module

uPSD34xx

252/293

firmware needs to be present for ISP. This is good for manufacturing, for field updates, and

for easy code development in the lab. JTAG-based programmers and debuggers for

uPSD34xx are available from STMicroelectronics and 3rd party vendors.

ISP is different than IAP (In-Application Programming). IAP involves the 8032 to program

Flash memory over any interface supported by the 8032 (e.g., UART, SPI, I2C), which is

good for remote updates over a communication channel. uPSD34xx devices support both

ISP and IAP. The entire PSD Module (Flash memory and PLD) may be programmed with

JTAG ISP, but only the Flash memories may be programmed using IAP.

28.6.2

JTAG chaining inside the package

JTAG protocol allows serial “chaining” of more than one device in a JTAG chain. The

uPSD34xx is assembled with a stacked die process combining the PSD Module (one die)

and the MCU Module (the other die). These two die are chained together within the

uPSD34xx package. The standard JTAG interface has four basic signals:

●

TDI - Serial data into device

●

TDO - Serial data out of device

●

TCK - Common clock

●

TMS - Mode Selection

Every device that supports IEEE 1149.1 JTAG communication contains a Test Access Port

(TAP) controller, which is a small state machine to manage JTAG protocol and serial

streams of commands and data. Both the PSD Module and the MCU Module each contain a

TAP controller.

Figure 91 illustrates how these die are chained within a package. JTAG programming/test

equipment will connect externally to the four IEEE 1149.1 JTAG pins on Port C. The TDI pin

on the uPSD34xx package goes directly to the PSD Module first, then exits the PSD Module

through TDO. TDO of the PSD Module is connected to TDI of the MCU Module. The serial

path is completed when TDO of the MCU Module exits the uPSD34xx package through the

TDO pin on Port C. The JTAG signals TCK and TMS are common to both modules as

specified in IEEE 1149.1. When JTAG devices are chained, typically one devices is in

BYPASS mode while another device is executing a JTAG operation. For the uPSD34xx, the

PSD Module is in BYPASS mode while debugging the MCU Module, and the MCU Module

is in BYPASS mode while performing ISP on the PSD Module.

The RESET_IN input pin on the uPSD34xx package goes to the MCU Module, and this

module will generate the RST reset signal for the PSD Module. These reset signals are

totally independent of the JTAG TAP controllers, meaning that the JTAG channel is

operational when the modules are held in reset. It is required to assert RESET_IN during

ISP. STMicroelectronics and 3rd party JTAG ISP tools will automatically assert a reset signal

during ISP. However, the user must connect this reset signal to RESET_IN as shown in

examples in Figure 92 on page 254 and Figure 93 on page 255.

UPSD3422 Datasheet(PDF) 252 Page - STMicroelectronics

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