UPSD3422 datasheet(268/293 Pages) STMICROELECTRONICS

268 / 293 page

DC and AC parameters

uPSD34xx

268/293

Table 158.

PSD module DC characteristics (with 3.3V VDD)

Note:

Internal PD is active.

PLD is in non-Turbo mode, and none of the inputs are switching.

Please see Figure 97 on page 260 for the PLD current calculation.

4IOUT = 0mA

Symb.

Parameter

Test Condition

(in addition to those in

Table 156 on page 265)

Min.

Typ.

Max.

Unit

VIH

High Level Input Voltage

3.0V < VDD < 3.6V

0.7VDD

VDD +0.5

VIL

Low Level Input Voltage

3.0V < VDD < 3.6V

–0.5

0.8

VLKO

VDD (min) for Flash

Erase and Program

1.5

2.2

VOL

Output Low Voltage

IOL = 20uA, VDD = 3.0V

0.01

0.1

IOL = 4mA, VDD = 3.0V

0.15

0.45

VOH

Output High Voltage

Except VSTBY On

IOH = –20uA, VDD = 3.0V

2.9

2.99

IOH = –1mA, VDD = 3.0V

2.7

2.8

VOH1

Output High Voltage

VSTBY On

IOH1 = 1uA

VSTBY –

0.8

VSTBY SRAM Stand-by Voltage

2.0

VDD

ISTBY

SRAM Stand-by Current

VDD = 0V

0.5

IIDLE

Idle Current (VSTBY

input)

VDD > VSTBY

–0.1

0.1

VDF

SRAM Data Retention

Voltage

Only on VSTBY

2VDD – 0.2

ISB

Stand-by Supply Current

for Power-down Mode

CSI > VDD – 0.3V

(Notes 1,2)

100

ILI

Input Leakage Current

VSS < VIN < VDD

–1

±0.1

ILO

Output Leakage Current

0.45 < VIN < VDD

–10

±5

ICC

(DC)

(Note

Operating

Supply

Current

PLD Only

PLD_TURBO = Off,

f = 0MHz (Note 2)

uA/P

PLD_TURBO = On,

f = 0MHz

200

400

uA/P

Flash

memory

During Flash memory

WRITE/Erase Only

Read only, f = 0MHz

SRAM

f = 0MHz

ICC

(AC)

(Note

PLD AC Adder

Note 3

Flash memory AC Adder

1.0

1.5

mA/

MHz

SRAM AC Adder

0.8

1.5

mA/

MHz

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