TMP93CS41 datasheet(54/248 Pages) TOSHIBA

54 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-52

(4) Notes

The instruction execution unit and the bus interface unit of this CPU operate

independently of each other. Therefore, if the instruction used to clear the interrupt

request flag of an interrupt is fetched before the interrupt is generated, it is possible

that the CPU might accept the interrupt and execute the fetched instruction to clear

the interrupt request flag while reading the interrupt vector. If so, the CPU would start

the interrupt processing from the address “8028H”.

To avoid the above occurring, clear the interrupt request flag by entering the

instruction to clear the flag after the DI instruction. In the case of setting an interrupt

enable again by EI instruction after the execution of clearing instruction, execute EI

instruction after clearing instruction and following more than one instruction are

executed. When EI instruction is placed immediately after clearing instruction, an

interrupt becomes enable before interrupt request flags are cleared.

In the case of changing the value of the interrupt mask register <IFF2:0> by

execution of POR SR instruction, disable an interrupt by DI instruction before

execution of POP SR instruction.

TMP93CS41 Datasheet(PDF) 54 Page - Toshiba Semiconductor