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TMP93CS44 Datasheet(PDF) 48 Page - Toshiba Semiconductor |
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TMP93CS44 Datasheet(HTML) 48 Page - Toshiba Semiconductor |
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48 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-46 (2) External interrupt control Interrupt Input Mode Control Register 7 6 5 4 3 2 1 0 Bit symbol − I0IE I0LE NMIREE IIMC (007BH) Read/Write W W After reset 0 0 0 0 Prohibit read- modify- write Function Always write “0”. 1: INT0 input enable 0: INT0 edge mode 1: INT0 level mode 1: Can be accepted in NMI rising edge. Note 1: The INT0 pin can also be used for standby release as described later. Even if the pin is not used for standby release, setting this register to “0” maintains the port function during standby mode. Note 2: Case of changing from level to edge for INT0 pin mode (<I0LE> “1” → “0” ) Execution example: LD (INTE0AD) , xxxx0000B ; INT0 disable, clean the request flag. LD (IIMC) , xxxxx10xB ; Change from level to edge. LD (INTE0AD) , xxxx0nnnB ; Set interrupt level “n” for INT0, clear the request flag. Note 3: IIMC<Bit7:3> is always read as “1”. Note 4: See electrical characteristics in section 4 for external interrupt input pulse. Figure 3.4.6 Interrupt Input Mode Control Register Table 3.4.2 Setting of External Interrupt Pin Functions Interrupt Shared Pin Mode Setting method Falling edge IIMC<NMIREE> = 0 NMI NMI (Dedicated pin) Falling and rising edges IIMC<NMIREE> = 1 Rising edge IIMC<I0LE> = 0, <I0IE> = 1 INT0 P35 Level IIMC<I0LE> = 1, <I0IE> = 1 INT1 P40 Rising edge − Rising edge T4MOD<CAP12M1:0> = 0, 0 or 0, 1 or 1, 1 INT4 P42 Falling edge T4MOD<CAP12M1:0> = 1, 0 INT5 P43 Rising edge − Rising edge T5MOD<CAP34M1:0> = 0, 0 or 0, 1 or 1, 1 INT6 P45 Falling edge T5MOD<CAP34M1:0> = 1, 0 INT7 P46 Rising edge − INT0 input enable (Note 1) 0 INT0 disable (P35 function only) 1 Input enable NMI rising edge enable 0 Interrupt request generation at falling edge 1 Interrupt request generation at rising/falling edge INT0 level enable (Note 2) 0 Rising edge detect interrupt 1 High level interrupt |
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