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TMP93CS44 Datasheet(PDF) 193 Page - Toshiba Semiconductor |
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TMP93CS44 Datasheet(HTML) 193 Page - Toshiba Semiconductor |
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193 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-191 4.3 AC Characteristics (1) VCC = 5 V ± 10% Variable 16 MHz 20 MHz No. Parameter Symbol Min Max Min Max Min Max Unit 1 Oscillation period ( = X) tOSC 50 31250 62.5 50 ns 2 CLK pulse width tCLK 2X − 40 85 60 ns 3 A0 to A23 valid → CLK hold tAK 0.5X − 20 11 5 ns 4 CLK valid → A0 to A23 hold tKA 1.5X − 70 24 5 ns 5 A0 to A15 valid → ALE fall tAL 0.5X − 15 16 10 ns 6 ALE fall → A0 to A15 hold tLA 0.5X − 20 11 5 ns 7 ALE high pulse width tLL X − 40 23 10 ns 8 ALE fall → RD / WR fall tLC 0.5X − 25 6 0 ns 9 RD / WR rise → ALE rise tCL 0.5X − 20 11 5 ns 10 A0 to A15 valid → RD / WR fall tACL X − 25 38 25 ns 11 A0 to A23 valid → RD / WR fall tACH 1.5X − 50 44 25 ns 12 RD / WR rise → A0 to A23 hold tCA 0.5X − 25 6 0 ns 13 A0 to A15 valid → D0 to D15 input tADL 3.0X − 55 133 95 ns 14 A0 to A23 valid → D0 to D15 input tADH 3.5X − 65 154 110 ns 15 RD fall → D0 to D15 input tRD 2.0X − 60 65 40 ns 16 RD low pulse width tRR 2.0X − 40 85 60 ns 17 RD rise → D0 to D15 hold tHR 0 0 0 ns 18 RD rise → A0 to A15 output tRAE X − 15 48 35 ns 19 WR low pulse width tWW 2.0X − 40 85 60 ns 20 D0 to D15 valid → WR rise tDW 2.0X − 55 70 45 ns 21 WR rise → D0 to D15 hold tWD 0.5X − 15 16 10 ns 22 A0 to A23 valid → WAIT input tAWH 3.5X − 90 129 85 ns 23 A0 to A15 valid → WAIT input tAWL 3.0X − 80 108 70 ns 24 RD / WR fall → WAIT hold tCW 2.0X + 0 125 100 ns 25 A0 to A23 valid → Port input tAPH 2.5X − 120 36 5 ns 26 A0 to A23 valid → Port hold tAPH2 2.5X + 50 206 175 ns 27 WR rise → Port valid tCP 200 200 200 ns AC measuring conditions • Output level: High 2.2 V, low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK) • Input level: High 2.4 V, low 0.45 V (AD0 to AD15) High 0.8 × VCC, low 0.2 × VCC (except for AD0 to AD15) (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode |
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