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Axelite Confidential Materials, do not copy or distribute without written consent.

Rev1.6 Oct.08, 2019

AX3070

PCB Layout Recommendations

VIN

COMP

FB

SEN2

SEN1

BS

LX

UG

LG

GND

AX3070

AX3071

C1

C4

Q1

Q2

L1

C6

R4

RS1

RS2

optional

R3

R2

C5

R1

C3

C2

C8

VIN

GND

VOUT

SEN1

SEN2

R7

R5

R6

C7

GND

R8

C9

1. PCB trace defined as LX node, which connects to source of switching MOSFET, drain of

rectifying MOSFET and high-voltage side of the inductor, should be as short and wide as

possible.

2. All sensitive analog traces such as SEN1, SEN2, COMP and FB should place away from

high-voltage switching nodes such as LX, UG or LG nodes to avoid coupling.

3. C8 input bypass capacitor should be placed to the VIN pin as close as possible.

4. Connections from the drivers to the respective gate of the high-side or the low-side

MOSFET should be as short as possible to reduce stray inductance. Use a 0.65 mm (25

mils) or wider trace.

5. Gather the ground terminals of the VIN capacitor(s), VOUT capacitor(s), and the source of the

low-side MOSFETs as close as possible. Signal ground and power ground should be

connected strongly together near the device.