All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

●

○

Single Design license for

VHDL, Verilog source code called HDL Sour-

ce

Encrypted, or plain text EDIF called Netlist

○

●

○

●

○

○

●

○

○

One Year license for

Encrypted Netlist only

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

HDL Source to Netlist

Single Design to Unlimited Designs

SYMBOL

datai(7:0)

irq

xirq

clk

addr(23:0)

ramwe

ramoe

por

cmf

halt

lir

prgdata(7:0)

prgaddr(15:0)

prgoe

ufrdatai(7:0)

ufraddr(7:0)

ufrwe

ufroe

ready

datao(7:0)

clkdocd

docddatai

docddatao

docdclk

prgwe

DoCD

PINS DESCRIPTI O N

PIN

ACTIVE

TYPE

DESCRIPTION

clk

-

input

Global system clock

por

Low

input

Power on Reset indicator

cmf

Low

input

Clock Monitor Fail Reset ID

prgdata[7:0]

-

input

Program memory bus input

ready

Low

input

Non-maskable interrupt input

datai[7:0]

-

input

External memory bus input

ufrdatai[7:0]

-

input

UFRs data bus input

irq

Low

input

Ready pin for CODE & DATA

xirq

Low

input

Non-maskable interrupt input

prgaddr[15:0]

-

output

Program memory address bus

prgoe

-

output

Program memory output enable

datao[7:0]

-

output

Data memory & UFR bus output

addr[23:0]

-

output

Data memory address bus

ramwe

Low

output

Data memory write enable

ramoe

Low

output

Data memory output enable

ufraddr[7:0]

-

output

FR address bus

ufrwe

Low

output

UFRs write enable

ufroe

Low

output

UFRs output enable

lir

Low

output

Load instruction register

halt

High

output

Halt clock system (STOP inst.)

clkdocd

-

input

Separate DoCD

docddatai

-

input

DoCD

docddatao

-

output

DoCD

docdclk

-

output

DoCD

prgwe

-

output

DoCD

* Kind of activity is configurable