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TMP88CS42FG Datasheet(PDF) 77 Page - Toshiba Semiconductor |
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TMP88CS42FG Datasheet(HTML) 77 Page - Toshiba Semiconductor |
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77 / 216 page  Page 67 TMP88CS42FG Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other modes) Note 6: Set TC1CR<TFF1> to “0” in the mode except PPG output mode. Note 7: Set TC1DRB after setting TC1CR<TC1M> to the PPG output mode. Note 8: When the STOP mode is entered, the start control (TC1CR<TC1S>) is cleared to “00” automatically, and the timer stops. After the STOP mode is exited, set the TC1CR<TC1S> to use the timer counter again. Note 9: Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Note 10:Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time. |
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