TMP86CS44UG datasheet(58/172 Pages) TOSHIBA

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Page 48

5. I/O Ports

TMP86CS44UG

5.1 Port P0 (P07 to P00)

Port P0 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output

and timer/counter input/output.

When used as an input port or a secondary function pins, the respective output latch (P0DR) should be set to “1”.

When used as an output port, the respective P0DR bit should be set data. During reset, the output latch is initialized

to “1”.

P0 port output latch (P0DR) and P0 port terminal input (P0PRD) are located on their respective address.

When read the output latch data, the P0DR should be read and when read the terminal input data, the P0PRD reg-

ister should be read. P00 port (INT0) can be configured as either an I/O port or as external interrupt input with

INT0EN (bit 6 in EINTCR). During reset, P00 port (INT0) is configured as an input port.

Figure 5-2 Port P0

P0DR

(0000H)

R/W

543

P07

INT4

P06

SCK

P05

P04

P03

TXD

P02

RXD

P01

PWM4

PDO4

PPG4

TC4

P00

INT0

(Initial value: 1111 1111)

P0PRD

(0008H)

Read only

543

P07

P06

P05

P04

P03

P02

P01

P00

Output latch

Port data (P0PRD)

Data output

Control output

STOP

OUTEN

Output latch data (P0DR)

Control input

P0i

Note:i=7 to 0

TMP86CS44UG Datasheet(PDF) 58 Page - Toshiba Semiconductor

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