TMP86FS49AIUG datasheet(83/296 Pages) TOSHIBA

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Page 67

TMP86FS49AIUG

Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”.

Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care

Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a

don’t care is read.

Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.

After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.

Note 5: To clear WDTEN, set the register in accordance with the procedures shown in “1.2.3 Watchdog Timer Disable”.

Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.

Note 2: *: Don’t care

Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.

Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.

6.2.2

Watchdog Timer Enable

Setting WDTCR1<WDTEN> to “1” enables the watchdog timer. Since WDTCR1<WDTEN> is initialized

to “1” during reset, the watchdog timer is enabled automatically after the reset release.

Watchdog Timer Control Register 1

WDTCR1

(0034H)

321

(ATAS)

(ATOUT)

WDTEN

WDTT

WDTOUT

(Initial value: **11 1001)

WDTEN

Watchdog timer enable/disable

0: Disable (Writing the disable code to WDTCR2 is required.)

1: Enable

Write

only

WDTT

Watchdog timer detection time

[s]

NORMAL1/2 mode

SLOW1/2

mode

Write

only

DV7CK = 0

DV7CK = 1

225/fc

217/fs

223/fc

215/fs

215fs

221fc

213/fs

213fs

219/fc

211/fs

WDTOUT

Watchdog timer output select

0: Interrupt request

1: Reset request

Write

only

Watchdog Timer Control Register 2

WDTCR2

(0035H)

543

(Initial value: **** ****)

WDTCR2

Write

Watchdog timer control code

4EH: Clear the watchdog timer binary counter (Clear code)

B1H: Disable the watchdog timer (Disable code)

D2H: Enable assigning address trap area

Others: Invalid

Write

only

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