TMP86FS49AIUG datasheet(245/296 Pages) TOSHIBA

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Page 229

TMP86FS49AIUG

Example :After chip erasure, the program in the RAM area writes data 3FH to address F000H.

: Disable interrupts (IMF

←"0")

(FLSCR),0011_1000B

: Enable command sequence execution.

IX,0F555H

IY,0FAAAH

HL,0F000H

; #### Flash Memory Chip erase Process ####

(IX),0AAH

: 1st bus write cycle

(IY),55H

: 2nd bus write cycle

(IX),80H

: 3rd bus write cycle

(IX),0AAH

: 4th bus write cycle

(IY),55H

: 5th bus write cycle

(IX),10H

: 6th bus write cycle

sLOOP1:

W,(IX)

CMP

W,(IX)

NZ,sLOOP1

: Loop until the same value is read.

SET

(FLSCR).3

: Set BANK1.

; #### Flash Memory Write Process ####

(IX),0AAH

: 1st bus write cycle

(IY),55H

: 2nd bus write cycle

(IX),0A0H

: 3rd bus write cycle

(HL),3FH

: 4th bus write cycle, (F000H)=3FH

sLOOP2:

W,(HL)

CMP

W,(HL)

NZ,sLOOP2

: Loop until the same value is read.

(FLSCR),1100_1000B

: Disable command sequence execution.

sLOOP3:

sLOOP3

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