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TMP86FS49AIUG Datasheet(PDF) 281 Page - Toshiba Semiconductor |
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TMP86FS49AIUG Datasheet(HTML) 281 Page - Toshiba Semiconductor |
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281 / 296 page  Page 265 TMP86FS49AIUG P67 P66 P65 P64 I/O Tri-state I/O R = 100 Ω (typ.) P63 P62 P61 P60 P7 I/O Tri-state I/O R = 100 Ω (typ.) Port I/O Input/Output Circuitry Remarks Data output Disable VDD R Initial "High-Z" Output latch input Key-on Wakeup Analog input Pin input Data output Disable VDD R Initial "High-Z" Output latch input Analog input Pin input |
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