TC74HC279AP/AF

2007-10-01

2

IEC Logic Symbol

R

&

S1

(2)

(3)

(1)

1S1

1S2

1R

(6)

2S

(5)

2R

(11)

3S1

S3

&

(12)

3S2

(10)

3R

R

(15)

(14)

4S

4R

(4)

(7)

(9)

(13)

1Q

2Q

3Q

4Q

R

R

S2

S4

1

2

3

4

Truth Table

Inputs

Output

S #

R

Q

H

H

Qn

L

H

H

H

L

L

L

L

H

Qn: The level of Q before the indicated input condition were established.

#: For latches with doubles S input.

H

= Both S input high

L

= One of both inputs low

System Diagram