MCP3912B datasheet(22/83 Pages) MICROCHIP

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MCP3912B

DS20006994A-page 22

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4.3

DMCLK – Digital Master Clock

This is the clock frequency that is present on the digital

portion of the device after prescaling and division by four

(the equation below). This is also the sampling

frequency, which is the rate at which the modulator

outputs are refreshed. Each period of this clock corre-

sponds to one sample and one modulator output. See

Figure 4-1.

EQUATION 4-2:

4.4

DRCLK – Data Rate Clock

This is the output data rate (i.e., the rate at which the

ADCs output new data). New data are signaled by a

data ready pulse on the DR pin.

This data rate is dependent on the OSR and the

prescaler with the formula in the equation below.

EQUATION 4-3:

There is a notch in the filter transfer function at each

integer multiple of this rate because this is the output

data rate and because the decimation filter is a SINC

(or notch) filter.

Table 4-2 describes the various combinations of OSR

and PRESCALE and their associated AMCLK, DMCLK

and DRCLK rates.

DMCLK

AMCLK

---------------------

MCLK

4 PRESCALE



----------------------------------------

DRCLK

DMCLK

OSR

----------------------

AMCLK

4OSR



---------------------

MCLK

4 OSR PRESCALE



-----------------------------------------------------------

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