20

NXP Semiconductors

33879

5.4.4

SPI integrity check

Checking the integrity of the SPI communication with the initial power-up of the VDD and EN pins is recommended. After initial system

start-up or reset, the MCU writes one 32-bit pattern to the 33879. The first 16 bits read by the MCU are 8 logic [0]s followed by the fault

status of the outputs. The second 16 bits are the same bit pattern sent by the MCU. By the MCU receiving the same bit pattern it sent,

bus integrity is confirmed. Note the second 16-bit pattern the MCU sends to the device is the command word and is transferred to the

outputs with rising edge of CS. Important: A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications.

SPI messages consisting of 16 SCLK pulses and multiples of 8 clock pulses thereafter are acknowledged. SPI messages consisting of

other than 16 + multiples of 8 SCLK pulses are ignored by the device.

5.4.5

Overtemperature fault

Overtemperature detection and shutdown circuits are specifically incorporated for each individual output. The shutdown following an

overtemperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155 °C

to 185 °C. When an output shuts down owing to an overtemperature fault, no other outputs are affected. The MCU recognizes the fault

by a one in the fault status register. After the 33879 device has cooled below the switch point temperature and 15 °C hysteresis, the output

activates unless otherwise told to shut down by the MCU via the SPI.

5.4.6

Overvoltage fault

An overvoltage condition on the VPWR pin causes the device to shut down all outputs until the overvoltage condition is removed. When

the overvoltage condition is removed, the outputs resume their previous state. This device does not detect an overvoltage on the VDD

pin. The overvoltage threshold on the VPWR pin is specified as VPWR(OV) V, with 1.0 V typical hysteresis. A VPWR overvoltage detection

is global, causing all outputs to be turned OFF.

5.4.7

Output off open load fault

An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit

programmed to a logic low state). The Output OFF Open Load fault is detected by comparing the drain-to-source voltage of the specific

MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. An output OFF open

load fault is indicated when the drain-to-source voltage is less than the output threshold voltage (VOUT(FLT-TH)) of 2.5 V to 4.0 V. Hence,

the 33879 declares the load open in the OFF state when the output drain-to-source voltage is less than VOUT(FLT-TH).

This device has an internal 80

μA current source connected from drain to source of the output MOSFET. The current source may be

programmed on or off via the SPI. The Power-ON Reset state for the current source is “off” and must be enabled via the SPI. To achieve

low Sleep mode quiescent currents, the open load detection current source of each driver is switched off when VDD or EN is removed.

During output switching, especially with capacitive loads, a false output OFF open load fault may be triggered. To prevent this false fault

from being reported, an internal fault filter of 100

μs to 300 μs is incorporated. A false fault reporting is a function of the load impedance,

RDS(on), COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer

times out before the fault comparator is enabled and the fault is detected. Once the condition causing the open load fault is removed, the

device resumes normal operation. The open load fault, however, is latched in the output DO register for the MCU to read.

5.4.8

Shorted load fault

A shorted load (overcurrent) fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater

than the current limit. There are two safety circuits progressively in operation during load short conditions providing system protection:

1. The device’s output current is monitored in an analog fashion using SENSEFET approach and current limited.

2. The device’s output thermal limit is sensed and when attained causes only the specific faulted output to shutdown. The output

remains off until cooled. The device then reasserts the output automatically. The cycle continues until fault is removed or the

command bit instructs the output off. Shorted load faults are reported properly through the SPI regardless of open load detection

current enable bits.

5.4.9

Undervoltage shutdown

An undervoltage condition on VDD or VPWR results in the shutdown of all outputs. The VDD undervoltage threshold is between 0.8 and

3.0 V. VPWR undervoltage threshold is between 3.0 V and 5.0 V. When the supplies fall below their respective thresholds, all outputs are

turned OFF. As both supplies returns to normal levels, internal logic is reset and the device resumes normal operation.