ST7LITE0XY0 datasheet(100/124 Pages) STMICROELECTRONICS

100 / 124 page

ST7LITE0xY0, ST7LITESxY0

100/124

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

TA = -40°C to 105°C, unless otherwise specified

Notes:

1. Data based on characterization results, not tested in production.

2. The IIO current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 82 and the

sum of IIO (I/O ports and control pins) must not exceed IVSS.

3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between

VILmax and VDD

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

VSS - 0.3

0.3xVDD

VIH

Input high level voltage

0.7xVDD

VDD + 0.3

Vhys

Schmitt trigger voltage hysteresis 1)

VOL

Output low level voltage 2)

VDD=5V

IIO=+5mA TA≤85°C

TA≤105°C

0.5

1.0

1.2

IIO=+2mA TA≤85°C

TA≤105°C

0.2

0.4

0.5

RON

Pull-up equivalent resistor 3) 1)

VDD=5V

Ω

tw(RSTL)out Generated reset pulse duration

Internal reset sources

µs

th(RSTL)in External reset pulse hold time

µs

tg(RSTL)in Filtered glitch duration

200

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