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Document number: BST-BMP384-DS003-11 Revision_1.0_112020

3.7.

Interrupts

The BMP384 provides an interrupt pin (INT), which allows to signal certain events to the host processor. Different events can

be mapped to the interrupt pin, which all are processed with a logical OR.

The available interrupts are listed below and can be read in the “INT_STATUS” register (see 4.3.8):

•

FIFO watermark interrupt

•

FIFO full interrupt

•

Data ready interrupt

3.7.1. Interrupt default mode

After a power-on or soft reset has completed, the interrupt pin is in push-pull and active high mode.

3.7.2. Interrupt pin latching

The chip can be operated in non-latched or latched mode:

•

Non-latched mode: Interrupts’ conditions are selected as a contributors to the INT pad. INT pad is de-asserted as

soon as the conditions of all the interrupts propagated to the INT pad are not valid.

For data ready, interrupt contribution is de-asserted by reading int_status or after 2.5ms after assertion of the

interrupt.

For FIFO interrupts, INT pad contributions are not affected by fifo_data readings, only by the interrupt conditions

•

Latched mode: Interrupt statuses are selected as contributors of the INT pad.

The minimum interrupt pulse width is Tint = 1µs

3.7.3. Monitoring

The status of interrupt bits is always visible in the “INT_STATUS” register. (see 4.3.8) for details.

3.7.4. Interrupt Pin Configuration

The interrupt pin / pad is configured by the Bits in the “INT_CTRL” register (see 4.3.14). However, the status bits are not

influenced thereby.

The output mode of the INT pad is controlled by int_od bit:

Table 19: int_od

int_od=’0’

Push-pull

int_od=’1’

Open-drain

The level of the interrupt pad can be configured and switched by int_level between active low and active high:

Table 20: int_level

int_level=’0’

active_low

int_level=’1’

active_high

The latching of interrupts for INT pad and INT_STATUS register can be enabled by int_latch=’1’ or disabled by int_latch=’0’.

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