| Electronic Components Datasheet Search |
|
BMM350 Datasheet(PDF) 44 Page - Bosch Sensortec GmbH |
|
|
|||||||||||||||||||||||||||||
BMM350 Datasheet(HTML) 44 Page - Bosch Sensortec GmbH |
|
44 / 63 page ![]() Bosch Sensortec | BST-BMM350-DS001-27 44 | 63 © Bosch Sensortec GmbH 2023 | All rights reserved, also regarding any disposal, exploitation, reproduction, editing, distribution, Document number: BST-BMM350-DS001-27 as well as in the event of applications for industrial property rights 9. Digital Interfaces The sensor supports the I²C and I3C digital interfaces, where it acts as a “slave” for both protocols. The I²C interface supports the Standard, Fast and Fast+ modes. The I3C interface supports the single-data-rate SDR, high data rate HDR is not supported. However, the device can detect entering HDR mode and immediately stops listening to I3C data traffic until it detects the “leave HDR” I3C message. The following transactions are supported: Single byte write Multiple byte write (using pairs of register addresses and register data) Single byte read Multiple byte read (using a single register address which is auto-incremented) I3C additionally supports in-band-interrupt IBI timing control ASYNC 9.1 Interface selection By default/after reset the I²C interface is active. After receiving the standardized I3C enable message (see I3C specification), the I3C interface is activated and remains active until a reset/power down event. The correct address must be applied in both communication modes. The I2C (legacy) address is a combination of a fixed value, the value of the level of the pin “ADSEL” at boot time (after reset). 9.2 I²C interface For detailed timings, please review the NXP original document UM10204.pdf (registration at https://www.nxp.com required). All modes (standard, fast, fast+) are supported. As the device does not perform clock stretching, the SCL structure is a high-Z input without open drain capability. The 5 MSB bits are fixed. The last bit is changeable by the pin setting of “ADSEL”. ADSEL will be evaluated at boot time, the I2C address is fixed then. The ADSEL pin must not be left floating; if left floating, the I²C address will be undefined. The 7-bit I2C device address is defined according to the following tables. Table 9: I2C address definition bit<6> bit <5> bit <4> bit <3> bit <2> bit <1> bit <0> 0 0 1 0 1 OTP backed, is 0 0: ADSEL=LOW By default bit 1 of the I2C address is 0. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |