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74GTL1655A Datasheet(PDF) 3 Page - STMicroelectronics |
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74GTL1655A Datasheet(HTML) 3 Page - STMicroelectronics |
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3 / 16 page ![]() Obsolete Product(s) - Obsolete Product(s) 74GTL1655A 3/16 Table 3: Function Table (1) 1) A to B data flow is shown. B to A flow is similar, but uses OEBA, LEBA and CLK 2) Output level before the indicated steady-state input conditions were established, provided that CLK was high before LEAB went low 3) Output level before the indicated steady-state input conditions were established Table 4: Output Enable Truth Table Table 5: B-Port Edge Rate Control (VERC) Truth Table INPUTS OUTPUT MODE OEAB LEAB CLK A B H XXX Z Isolation L H X L L Transparent L H X H H Transparent LL LL Registered L L H H Registered LL H X B0(2) Previous State LLL X B0(3) Previous State INPUTS OUTPUTS OE OEAB OEBA A PORT B PORT L L L Active Active LL H Z Active LHL Active Z LH H Z Z HX X Z Z INPUT VERC OUTPUT B PORT EDGE RATE LOGIC LEVEL NOMINAL VOLTAGE H VCC Slow LGND Fast |
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