ASIX ELECTRONICS CORPORATION

6

AX88772A/AX88172A

Low-pin-count

USB 2.0 to 10/100M Fast Ethernet Controller

Table of Contents

1.0

INTRODUCTION...................................................................................................................9

1.1

GENERAL DESCRIPTION....................................................................................................................................... 9

1.2

BLOCK DIAGRAM ................................................................................................................................................ 9

1.3

PINOUT DIAGRAM.............................................................................................................................................. 10

2.0

SIGNAL DESCRIPTION ...........................................................................................14

2.1

AX88772A 64-PIN PINOUT DESCRIPTION ......................................................................................................... 14

2.2

AX88172A 80-PIN PINOUT DESCRIPTION ......................................................................................................... 16

2.3

HARDWARE SETTING FOR OPERATION MODE AND MULTI-FUNCTION PINS...................................................... 20

3.0

FUNCTION DESCRIPTION.................................................................................20

3.1

USB CORE AND INTERFACE .............................................................................................................................. 20

3.2

10/100M ETHERNET PHY................................................................................................................................. 20

3.3

MAC CORE ....................................................................................................................................................... 20

3.4

OPERATION MODE............................................................................................................................................. 20

3.5

STATION MANAGEMENT (STA)......................................................................................................................... 20

3.6

MEMORY ARBITER ............................................................................................................................................ 20

3.7

USB TO ETHERNET BRIDGE .............................................................................................................................. 20

3.8

SERIAL EEPROM LOADER ............................................................................................................................... 20

3.9

GENERAL PURPOSE I/O...................................................................................................................................... 20

3.10

SERIAL INTERFACE CONTROLLER...................................................................................................................... 20

3.11

CLOCK GENERATION ......................................................................................................................................... 20

3.12

RESET GENERATION .......................................................................................................................................... 20

3.13

VOLTAGE REGULATOR ...................................................................................................................................... 20

4.0

SERIAL EEPROM MEMORY MAP ........................................................20

4.1

DETAILED DESCRIPTION .................................................................................................................................... 20

5.0

USB CONFIGURATION STRUCTURE ..............................................20

5.1

USB CONFIGURATION....................................................................................................................................... 20

5.2

USB INTERFACE................................................................................................................................................ 20

5.3

USB ENDPOINTS ............................................................................................................................................... 20

6.0

USB COMMANDS...............................................................................................................20

6.1

USB STANDARD COMMANDS............................................................................................................................ 20

6.2

USB VENDOR COMMANDS................................................................................................................................ 20

6.2.1

Detailed Register Description .................................................................................................................. 20

6.2.2

Command Block Wrapper for Serial Interface ......................................................................................... 20

6.2.2.1

UART controller ................................................................................................................................. 20

6.2.2.2

I2C controller ...................................................................................................................................... 21

6.2.2.3

SPI controller ...................................................................................................................................... 21

6.3

INTERRUPT ENDPOINT ....................................................................................................................................... 21

7.0

EMBEDDED ETHERNET PHY REGISTER

DESCRIPTION ........................................................................................................................................21

7.1

PHY REGISTER DETAILED DESCRIPTION........................................................................................................... 21

7.1.1

Basic Mode Control Register (BMCR) ..................................................................................................... 21

7.1.2

Basic Mode Status Register (BMSR)......................................................................................................... 21

7.1.3

PHY Identifier Register 1.......................................................................................................................... 21