FS32K112BFT0M datasheet(55/85 Pages) NXP

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Table 32. LPSPI electrical specifications1 (continued)

Num

Symbol

Description

Conditions

Run Mode2

HSRUN Mode2

VLPR Mode

Unit

5.0 V IO

3.3 V IO

5.0 V IO

3.3 V IO

5.0 V IO

3.3 V IO

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Master

Loopback(slow)

Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.

While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz.

fperiph = LPSPI peripheral clock

tperiph = 1/fperiph

Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.

Clock pads used are PTD15 and PTE0. Applicable only for LPSPI0.

Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.

Clock pad used is PTB2. Applicable only for LPSPI0.

This is the maximum operating frequency (fop) for LPSPI0 with medium PAD type only. Otherwise, the maximum operating frequency (fop) is 12 Mhz.

Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges from 0 to 255.

Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges from 0 to 255.

10.

While selecting odd dividers, ensure Duty Cycle is meeting this parameter.

11.

Maximum operating frequency (fop ) is 12 MHz irrespective of PAD type and LPSPI instance.

12.

Applicable for LPSPI0 only with medium PAD type, with maximum operating frequency (fop) as 14 MHz.

FS32K112BFT0M Datasheet(PDF) 55 Page - NXP Semiconductors

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