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STM32G474CB Datasheet(PDF) 200 Page - STMicroelectronics

Part # STM32G474CB
Description  Arm® Cortex®-M4 32b MCUFPU, up to 512 KB Flash, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math accelerator, 184ps 12ch Hi-res timer
PDF  232 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G474CB Datasheet(HTML) 200 Page - STMicroelectronics

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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
200/232
DS12288 Rev 1
Figure 51. Quad SPI timing diagram - SDR mode
tw(CKH) Quad SPI clock high
and low time
Even division
PRESCALER [7:0]
n =0,1, 3, 5 ...
t(CK)/2
-
t(CK)/2+1
ns
tw(CKL)
t(CK)/2-1
-
t(CK)/2
tw(CKH) Quad SPI clock high and
low time
Odd division
PRESCALER [7:0]
n =2,4, 6, 8...
(n/2)*t(CK)/(n+1)
-
(n/2)*t(CK)/(n+1) + 1
tw(CKL)
(n/2+1)*t(CK)/(n+1) - 1
-
(n/2+1)*t(CK)/(n+1)
tsh(IN)
Data input setup time on
rising edge
1.71 < VDD< 3.6 V
1
-
-
tsl(IN)
Data input setup time on
falling edge
1.71 < VDD< 3.6 V
1
-
-
thh(IN)
Data input hold time on
rising edge
1.71 < VDD< 3.6 V
6
-
-
thl(IN)
Data input hold time on
falling edge
1.71 < VDD< 3.6 V
5
-
-
tvh(OUT)
Data output valid time on
rising edge
1.71 < VDD< 3.6 V
DHHC = 0
-
7.5
8
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2
+1
Thclk/2+1.5
tvf(OUT) Data output valid time
1.71 < VDD< 3.6 V
DHHC = 0
-
710
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2
+1
Thclk/2+2
thh(OUT)
Data output hold time on
rising edge
1.71 < VDD< 3.6 V
DHHC = 0
2-
-
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2+ 0.5
-
thf(OUT)
Data output hold time on
falling edge
1.71 < VDD< 3.6 V
DHHC = 0
3-
-
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2+0.5
-
1. Guaranteed by characterization results.
Table 109. QUADSPI characteristics in DDR mode(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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