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VLSI
Solution
y
VS1103b
VS1103B
8. VS1103B REGISTERS
0000
0000
Instruction (32−bit)
Y (16−bit)
X (16−bit)
System Vectors
User
Instruction
RAM
X DATA
RAM
Y DATA
RAM
0030
0030
Y DATA
ROM
X DATA
ROM
4000
4000
Instruction
ROM
Hardware
Register
Space
C000
C100
C100
C000
0500
0500
8000
8000
1E00
1E00
1C00
1C00
Stack
Stack
User
Space
User
Space
1940
1880
1800
1800
1880
1940
Figure 14: User’s Memory Map.
8.6 DAC Registers
DAC registers, prefix DAC
Reg
Type
Reset
Abbrev[bits]
Description
0xC013
rw
0
FCTLL
DAC frequency control, 16 LSbs.
0xC014
rw
0
FCTLH
DAC frequency control 4MSbs, PLL control.
0xC015
rw
0
LEFT
DAC left channel PCM value.
0xC016
rw
0
RIGHT
DAC right channel PCM value.
Every fourth clock cycle, an internal 26-bit counter is added to by (DAC FCTLH & 15) × 65536 +
DAC FCTLL. Whenever this counter overflows, values from DAC LEFT and DAC RIGHT are read and
a DAC interrupt is generated.
Version 1.01, 2007-09-03
46
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