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STM32G474CBH3 Datasheet(PDF) 19 Page - STMicroelectronics

Part # STM32G474CBH3
Description  Arm® Cortex®-M4 32b MCUFPU, up to 512 KB Flash, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math accelerator, 184ps 12ch Hi-res timer
PDF  232 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G474CBH3 Datasheet(HTML) 19 Page - STMicroelectronics

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DS12288 Rev 1
19/232
STM32G474xB STM32G474xC STM32G474xE
Functional overview
47
3.5
Embedded SRAM
STM32G474xB/xC/xE devices feature 128 Kbytes of embedded SRAM. This SRAM is split
into three blocks:
•
80 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the
SRAM1 through the System Bus or through the I-Code/D-Code bus. The first 32 Kbyte
of SRAM1 support hardware parity check.
•
16 Kbytes mapped at address 0x2001 4000 (SRAM2). The CM4 can access the
SRAM2 through the System Bus or through the I-Code/D-Code bus. SRAM2 can be
retained in standby modes.
•
32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU
through I-Code/D-Code bus for maximum performance.
It is also aliased at 0x2001 8000 address to be accessed by all masters (CPU, DMA1,
DMA2) through SBUS contiguously to SRAM1 and SRAM2. The CCM SRAM supports
hardware parity check and can be write-protected with 1 Kbyte granularity.
•
The memory can be accessed in read/write at max CPU clock speed with 0 wait states.



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