DAC7611P datasheet(10/18 Pages) TI2

10 / 18 page

DAC7611

clear input (CLR) is provided to simplify start-up or periodic

resets. Table I shows the relationship between input code

and output voltage.

The digital data into the DAC7611 is double-buffered. This

means that new data can be entered into the DAC without

disturbing the old data and the analog output of the con-

verter. At some point after the data has been entered into the

serial shift register, this data can be transferred into the DAC

transition of the LD pin. However, the LD pin makes the

DAC register transparent. If new data is shifted into the shift

change as each new bit is entered. To prevent this, LD must

be returned HIGH prior to shifting in new serial data.

At any time, the contents of the DAC register can be set to

000H (analog output equals 0V) by taking the CLR input

LOW. The DAC register will remain at this value until CLR

is returned HIGH and LD is taken LOW to allow the

contents of the shift register to be transferred to the DAC

H and the analog output driven to

0V. When CLR is returned HIGH, the DAC register will be

set to the current value in the serial shift register and the

analog output will respond accordingly.

DIGITAL-TO-ANALOG CONVERTER

The internal DAC section is a 12-bit voltage output

device that swings between ground and the internal ref-

erence voltage. The DAC is realized by a laser-trimmed

R-2R ladder network which is switched by N-channel

MOSFETs. The DAC output is internally connected to

the rail-to-rail output operational amplifier.

OUTPUT AMPLIFIER

A precision, low-power amplifier buffers the output of the

DAC section and provides additional gain to achieve a 0 to

4.095V range. The amplifier has low offset voltage, low

noise, and a set gain of 1.682V/V (4.095/2.435). See Figure

2 for an equivalent circuit schematic of the analog portion of

the DAC7611.

FIGURE 2. Simplified Schematic of Analog Portion.

OPERATION

The DAC7611 is a 12-bit digital-to-analog converter (DAC)

complete with a serial-to-parallel shift register, DAC regis-

ter, laser-trimmed 12-bit DAC, on-board reference, and a

rail-to-rail output amplifier. Figure 1 shows the basic opera-

tion of the DAC7611.

INTERFACE

Figure 1 shows the basic connection between a

microcontroller and the DAC7611. The interface consists of

a serial clock (CLK), serial data (SDI), and a load strobe

signal (LD). In addition, a chip select (CS) input is available

to enable serial communication when there are multiple

serial devices. The data format is Straight Binary and is

loaded MSB-first into the shift registers. An asynchronous

DAC7611 Full-Scale Range = 4.095V

Least Significant Bit = 1mV

DIGITAL INPUT CODE

ANALOG OUTPUT

STRAIGHT BINARY

(V)

DESCRIPTION

FFFH

+4.095

Full Scale

801H

+2.049

Midscale + 1 LSB

800H

+2.048

Midscale

7FFH

+2.047

Midscale – 1 LSB

000H

Zero Scale

TABLE I. Digital Input Code and Corresponding Ideal

Analog Output.

FIGURE 1. Basic Operation of the DAC7611.

Output Amplifier

R-2R DAC

Bandgap

Reference

2.435V

Buffer

OUT

GND

CLR

CLK

SDI

Serial Clock

Serial Data

Load Strobe

DAC7611

0.1µF

10µF

From

µC

0V to

+4.095V

+5V

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