March 26, 2021

3.2

ES9016K2M Datasheet

5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-

8800 • www.esstech.com

FUNCTIONAL DESCRIPTION

NOTATATIONS for Sampling Rates

Mode

fs (target sample rate)

FSR (raw sample rate)

DSD

DATA_CLK / 64

DSD data rate

Serial (PCM) Normal Mode

Frame Clock Rate

Frame Clock Rate

Serial (PCM) OSF Bypass Mode

Frame Clock Rate / 8

Frame Clock Rate

SPDIF

SPDIF Sampling Rate

SPDIF Sampling Rate

PCM, SPDIF and DSD Pin Connections

PCM Audio Format

Notes:

XI clock (MCLK) must be > 192 x FSR when using PCM input (normal mode), or 128 x FSR (synchronous MCLK).

XI clock (MCLK) must be > 24 x FSR when using PCM input (OSF bypass mode).

Pin Name

Description

DATA1

Frame clock

DATA2

2-channel PCM serial data

DATA_CLK

Bit clock for PCM audio format

Master Mode (32-bit data only)

W

hen Register #1 ‘input_select’ is set to 2’d0 (I2S) and ‘i2s_length’ is set to 2’d2 (32-bit), the DAC can become a

master for Bit Clock and Frame

Clock by setting Register #9 ‘master clock enable’ to 1’b1. The Bit Clock frequency

can be configured to MCLK / 4, MCLK / 8 or MCLK /

16 by setting Register #9 ‘clock divider select’ to 2’b00, 2’b01 or

2’b10. GPIO 1 can be configured to output MCLK by setting Register #8 gpio1_cfg to 4’d3.

DATA_CLK

DATA1

DATA2

SIN (Serial PCM Data)

ES901xK2M

DATA_CLK

DATA1

DATA2

ES901xK2M

GPIO1

MCLK (Master Clock)

SLAVE PCM MODE

MASTER PCM MODE

BCLK (Bit Clock)

LRCLK (Frame Clock)

BCLK (Bit Clock)

LRCLK (Frame Clock)

SIN (Serial PCM Data)

SPDIF Audio Formant

Note: XI clock (MCLK) must be > 386 x FSR when using SPDIF input.

Up to four SPDIF inputs can be connected to the 4-to-

1 mux, selectable via register “spdif_sel”. SPDIF can also be sourced

from a GPIO pin configured as input.

Pin Name

Description

GPIO1

SPDIF input 4

DATA1

SPDIF input 3

DATA2

SPDIF input 2

DATA_CLK

SPDIF input 1

DSD Audio Format

Note: XI clock (MCLK) must be > 3 x FSR when using DSD input.

Pin Name

Description

DATA[1:2]

2-channel DSD data input

DATA_CLK

Bit clock for DSD data input