SLG46533M datasheet(50/189 Pages) RENESAS

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SLG46533

Revision 1.30

8.2

Matrix Output Table

Table 38. Matrix Output Table

Address

Matrix Output Signal Function

Note: For each Address, the two most significant bits are unused)

Matrix Output

Number

reg <7:0>

Matrix OUT: IN0 of 3-bit LUT11 or Clock Input of DFF8

reg <15:8>

Matrix OUT: IN1 of 3-bit LUT11 or Data Input of DFF8

reg <23:16>

Matrix OUT: IN2 of 3-bit LUT11 or nRST (nSET) of DFF82

reg <31:24>

Matrix OUT: IN0 of 3-bit LUT12 or Clock Input of DFF93

reg <39:32>

Matrix OUT: IN1 of 3-bit LUT12 or Data Input of DFF9

reg <47:40>

Matrix OUT: IN2 of 3-bit LUT12 or nRST (nSET) of DFF95

reg <55:48>

Matrix OUT: IN0 of 3-bit LUT13 or Clock Input of DFF10

reg <63:56>

Matrix OUT: IN1 of 3-bit LUT13 or Data Input of DFF107

reg <71:64>

Matrix OUT: IN2 of 3-bit LUT13 or nRST (nSET) of DFF10

reg <79:72>

Matrix OUT: IN0 of 3-bit LUT14 or Clock Input of DFF11

reg <87:80>

Matrix OUT: IN1 of 3-bit LUT14 or Data Input of DFF1110

reg <95:88>

Matrix OUT: IN2 of 3-bit LUT14 or nRST (nSET) of DFF11

reg <103:96>

Matrix OUT: IN0 of 3-bit LUT15 or Clock Input of DFF12

reg <111:104>

Matrix OUT: IN1 of 3-bit LUT15 or Data Input of DFF12

reg <119:112>

Matrix OUT: IN2 of 3-bit LUT15 or nRST (nSET) of DFF12

reg <127:120>

Matrix OUT: IN0 of 3-bit LUT16 or Clock Input of DFF13

reg <135:128>

Matrix OUT: IN1 of 3-bit LUT16 or Data Input of DFF13

reg <143:136>

Matrix OUT: IN2 of 3-bit LUT16 or nRST (nSET) of DFF13

reg <151:144>

Matrix OUT: IN0 of 3-bit LUT17 or Clock Input of DFF14

reg <159:152>

Matrix OUT: IN1 of 3-bit LUT17 or Data Input of DFF14

reg <167:160>

Matrix OUT: IN2 of 3-bit LUT17 or nRST (nSET) of DFF14

reg <175:168>

Matrix OUT: IN0 of 4-bit LUT2

reg <183:176>

Matrix OUT: IN1 of 4-bit LUT2

reg <191:184>

Matrix OUT: IN2 of 4-bit LUT2

reg <199:192>

Matrix OUT: IN3 of 4-bit LUT2

reg <207:200>

Matrix OUT: IO1 Digital Output Source

reg <215:208>

Matrix OUT: IO1 Output Enable

reg <223:216>

Matrix OUT: IO2 Digital Output Source

reg <231:224>

Matrix OUT: IO3 Digital Output Source

reg <239:232>

Matrix OUT: IO3 Output Enable

reg <247:240>

Matrix OUT: IO4 Digital Output Source

reg <255:248>

Matrix OUT: IO5 Digital Output Source

reg <263:256>

Matrix OUT: IO5 Output Enable

reg <271:264>

Matrix OUT: IO6 Digital Output Source (SCL with VI/Input & NMOS open-drain)

reg <279:272>

Matrix OUT: IO7 Digital Output Source (SDA with VI/Input & NMOS open-drain)

reg <287:280>

Matrix OUT: IO8 Digital Output Source

reg <295:288>

Matrix OUT: IO8 Output Enable

reg <303:296>

Matrix OUT: IO9 Digital Output Source

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