LM2773

SNVS554A – JANUARY 2008 – REVISED MAY 2013

www.ti.com

Electrical Characteristics

(1) (2)

Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the full operating junction temperature range

(-30°C

≤ TJ ≤ +110°C) . Unless otherwise noted, specifications apply to the LM2773 Typical Application Circuit (pg. 1) with:

VIN = 3.6V; V(EN) = 1.8V, V(SEL) = 0V, CIN = C1 = C2 = 1.0µF, COUT = 4.7µF.

(3)

Symbol

Parameter

Condition

Min

Typ

Max

Units

1.8V Mode Output Voltage

2.5V

≤ VIN ≤ 5.5V

1.779

1.851

1.815

Regulation

0mA

≤ IOUT ≤ 300mA

(

−2%)

(+2%)

VOUT

V

V(SEL) = 1.8V

1.6V Mode Output Voltage

1.587

1.651

2.5V

≤ VIN ≤ 5.5V

1.619

Regulation

(

−2%)

(+2%)

0mA

≤ IOUT ≤ 300mA

VOUT/IOUT

Output Load Regulation

0mA

≤ IOUT ≤ 300mA

0.15

mV/mA

VOUT/VIN

Output Line Regulation

0.3

%/V

E

Power Efficiency

IOUT = 300mA

75

%

IOUT = 0mA

IQ

Quiescent Supply Current

48

55

µA

See(4)

VR

Fixed Frequency Output Ripple

IOUT = 300mA

10

mV

VR–PFM

PFM–Mode Output Ripple

IOUT < 40mA

12

mV

ISD

Shutdown Current

V(EN) = 0V

0.1

0.625

µA

FSW

Switching Frequency

3.0V

≤ VIN ≤ 5.5V

0.80

1.15

1.50

MHz

ROL

Open-Loop Output Resistance

IOUT = 300mA

1.0

Ω

See(5)

VIN = 5.5V

ICL

Output Current Limit

0V

≤ VOUT ≤ 0.2V

500

mA

See(6)

tON

Turn-on Time

150

µs

EN, SEL Pins

VIL

Logic-low Input Voltage

0

0.5

V

2.5V

≤ VIN ≤ 5.5V

EN, SEL Pins

VIH

Logic-high Input Voltage

1.0

VIN

V

2.5V

≤ VIN ≤ 5.5V

V(EN), V(SEL) = 1.8V

IIH

Logic-high Input Current

5

µA

See(7)

IIL

Logic-low Input Current

V(EN), V(SEL) = 0V

0.01

µA

(1)

All voltages are with respect to the potential at the GND pins.

(2)

Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most

likely norm.

(3)

CIN, COUT, C1, C2: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4)

VOUT is set to 1.9V during this test (Device is not switching).

(5)

Open loop output resistance can be used to predict output voltage when, under low VIN and high IOUT conditions, VOUT falls out of

regulation. VOUT = (Gain)VIN - (ROL x IOUT)

(6)

Under the stated conditions, the maximum input current is equal to 2/3 the maximum output current.

(7)

There are 350k

Ω pull-down resistors connected internally between the EN pin and GND and the SEL pin and GND.

4

Submit Documentation Feedback

Copyright © 2008–2013, Texas Instruments Incorporated

Product Folder Links: LM2773