CRMIX

HS

Phase or CLK

Leading Edge

Modulation

CV

RAMP

RAMP

55k

COMP

PWM

40k

100k

0.7V

CLK

Isync x 3

CRMIX

CV

BUFFER

FB

0.75V

TRK/SS

ERROR

AMP

CRAMP

LM5115A

SNVS467B – DECEMBER 2006 – REVISED MARCH 2013

www.ti.com

Vphase = 10V

CH1 = Master output, 1V/Div

CH2 = COMP, 5/Div

CH3 = Iout, 1A/Div

CH4 = SSPR Output (Slave), 1V/Div

Horizontal Resolution= 200 µs/Div

Figure 18. Tracking with Equal Slew Rate

Leading Edge Pulse Width Modulation

Unlike conventional voltage mode controllers, the LM5115A implements leading edge pulse width modulation. A

current source equal to 3 times the ISYNC current is used to charge the capacitor connected to the RAMP pin as

shown in Figure 19. The ramp signal and the output of the error amplifier (COMP) are combined through a

resistor network to produce a voltage ramp with variable dc offset (CRMIX in Figure 19). The high-side MOSFET

which drives the HS pin is held in the off state at the beginning of the phase signal. When the voltage of CRMIX

exceeds the internal threshold voltage CV, the PWM comparator turns on the high-side MOSFET. The HS pin

rises and the MOSFET delivers current from the main converter phase signal to the output of the auxiliary

regulator. The PWM cycle ends when the phase signal falls and power is no longer supplied to the drain of the

high-side MOSFET.

Leading edge modulation of the auxiliary PWM controller is required if the main converter uses peak current

mode control. If trailing edge modulation were used, the additional load on the transformer secondary from the

auxiliary channel would be drawn only during the first portion of the phase signal pulse. Referring to Figure 20,

the turn-off of the high- side MOSFET of the auxiliary regulator would create a non-monotonic negative step in

the transformer current. This negative current step would produce instability in a peak current mode controller.

With leading edge modulation, the additional load presented by the auxiliary regulator on the transformer

secondary will be present during the latter portion of the phase signal. This positive step in the phase signal

current can be accommodated by a peak current mode controller without instability.

Figure 19. Synchronization and Leading Edge Modulation

14

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