LM5115

SNVS343E – MARCH 2005 – REVISED MARCH 2013

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A current limit fold-back feature is provided by the LM5115 to reduce the peak output current delivered to a

shorted load. When the common mode input voltage to the current sense amplifier (CS and VOUT pins) falls

below 2V, the current limit threshold is reduced from the normal level. At common mode voltages > 2V, the

current limit threshold is nominally 45mV. When VOUT is reduced to 0V the current limit threshold drops to 36mV

to reduce stress on the inductor and power MOSFETs.

Negative Current Limit

When inductor current flows from the regulator output through the low side MOSFET, the input to the current

sense comparator becomes negative. The intent of the negative current comparator is to protect the low side

MOSFET from excessive currents. Negative current can lead to large negative voltage spikes on the output at

turn off which can damage circuitry powered by the output. The negative current comparator threshold is

sufficiently negative to allow inductor current to reverse at no load or light load conditions. It is not intended to

support discontinuous conduction mode with diode emulation by the low side MOSFET. The negative current

comparator shown illustrated in Figure 17 monitors the CV signal and compares this signal to a fixed 1V

threshold. This corresponds to a negative VCL voltage between CS and VOUT of -17mV. The negative current

limit comparator turns off the low side MOSFET for the remainder of the cycle when the VCL input falls below this

threshold.

Gate Drivers Outputs (HO & LO)

The LM5115 provides two gate driver outputs, the floating high side gate driver HO and the synchronous rectifier

low side driver LO. The low side driver is powered directly by the VCC regulator. The high side gate driver is

powered from a bootstrap capacitor connected between HB and HS. An external diode connected between VCC

and HB charges the bootstrap capacitor when the HS is low. When the high side MOSFET is turned on, HB rises

with HS to a peak voltage equal to VCC + VHS - VD where VD is the forward drop of the external bootstrap diode.

Both output drivers have adaptive dead-time control to avoid shoot through currents. The adaptive dead-time

control circuit monitors the state of each driver to ensure that the opposing MOSFET is turned off before the

other is turned on. The HB and VCC capacitors should be placed close to the pins of the LM5115 to minimize

voltage transients due to parasitic inductances and the high peak output currents of the drivers. The

recommended range of the HB capacitor is 0.047µF to 0.22µF.

Both drivers are controlled by the PWM logic signal from the PWM latch. When the phase signal is low, the

outputs are held in the reset state with the low side MOSFET on and the high side MOSFET off. When the phase

signal switches to the high state, the PWM latch reset signal is de-asserted. The high side MOSFET remains off

until the PWM latch is set by the PWM comparator (CRMIX > CV as shown in Figure 15). When the PWM latch

is set, the LO driver turns off the low side MOSFET and the HO driver turns on the high side MOSFET. The high

side pulse is terminated when the phase signal falls and SYNC input comparator resets the PWM latch.

Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction

temperature limit is exceeded. When activated, typically at 165 degrees Celsius, the controller is forced into a low

power standby state with the output drivers and the bias regulator disabled. The device will restart when the

junction temperature falls below the thermal shutdown hysteresis, which is typically 25 degrees. The thermal

protection feature is provided to prevent catastrophic failures from accidental device overheating.

Standalone DC/DC Synchronous Buck Mode

The LM5115 can be configured as a standalone DC/DC synchronous buck controller. In this mode the LM5115

uses leading edge modulation in conjunction with valley current mode control to control the synchronous buck

power stage. The internal oscillator within the LM5115 sets the clock frequency for the high and low side drivers

of the external synchronous buck power MOSFETs . The clock frequency in the synchronous buck mode is

programmed by the SYNC pin resistor and RAMP pin capacitor. Connecting a resistor between a dc bias supply

and the SYNC pin produces a current, ISYNC, which sets the charging current of the RAMP pin capacitor . The

RAMP capacitor is charged until its voltage reaches the peak ramp threshold of 2.25V. The RAMP capacitor is

then discharged for 300ns before beginning a new PWM cycle. The 300ns reset time of the RAMP pin sets the

minimum off time of the PWM controller in this mode. The internal clock frequency in the synchronous buck

mode is set by ISYNC, the ramp capacitor, the peak ramp threshold, and the 300ns deadtime.

FCLK ≊ 1 / ((CRAMP x 2.25V) / (ISYNC x 3) + 300ns)

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