DS91C176, DS91D176

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SNLS146L – MARCH 2006 – REVISED APRIL 2013

Absolute Maximum Ratings

(1) (2)

Supply Voltage, VCC

−0.3V to +4V

Control Input Voltages

−0.3V to (VCC + 0.3V)

Driver Input Voltage

−0.3V to (VCC + 0.3V)

Driver Output Voltages

−1.8V to +4.1V

Receiver Input Voltages

−1.8V to +4.1V

Receiver Output Voltage

−0.3V to (VCC + 0.3V)

Maximum Package Power Dissipation at +25°C

SOIC Package

833 mW

Derate SOIC Package

6.67 mW/°C above +25°C

Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)

θJA

150°C/W

θJC

63°C/W

Maximum Junction Temperature

150°C

Storage Temperature Range

−65°C to +150°C

Lead Temperature

(Soldering, 4 seconds)

260°C

ESD Ratings:

(HBM 1.5k

Ω, 100pF)

≥ 8 kV

(EIAJ 0

Ω, 200pF)

≥ 250 V

(CDM 0

Ω, 0pF)

≥ 1000 V

(1)

“Absolute Maximum Ratings” are those beyond which the safety of the device cannot be verified. They are not meant to imply that the

device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.

(2)

If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

Recommended Operating Conditions

Min

Typ

Max

Units

Supply Voltage, VCC

3.0

3.3

3.6

V

Voltage at Any Bus Terminal (Separate or Common-Mode)

−1.4

+3.8

V

Differential Input Voltage VID

2.4

V

LVTTL Input Voltage High VIH

2.0

VCC

V

LVTTL Input Voltage Low VIL

0

0.8

V

Operating Free Air Temperature TA

−40

+25

+85

°C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2) (3) (4)

Parameter

Test Conditions

Min

Typ

Max

Units

M-LVDS Driver

|VAB|

Differential output voltage magnitude

RL = 50Ω, CL = 5pF

480

650

mV

See Figure 4 and Figure 6

ΔVAB

Change in differential output voltage magnitude

−50

0

+50

mV

between logic states

VOS(SS)

Steady-state common-mode output voltage

RL = 50Ω, CL = 5pF

0.3

1.8

2.1

V

See Figure 4 and Figure 5

|

ΔVOS(SS)|

Change in steady-state common-mode output

0

+50

mV

(VOS(PP) @ 500KHz clock)

voltage between logic states

VOS(PP)

Peak-to-peak common-mode output voltage

135

mV

VA(OC)

Maximum steady-state open-circuit output voltage

See Figure 7

0

2.4

V

VB(OC)

Maximum steady-state open-circuit output voltage

0

2.4

V

(1)

All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless

otherwise specified.

(2)

All typicals are given for VCC = 3.3V and TA = 25°C.

(3)

The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.

(4)

CL includes fixture capacitance and CD includes probe capacitance.

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