LMK03002

www.ti.com

SNAS414E – AUGUST 2007 – REVISED APRIL 2013

PLL_MUX[3:0] – Multiplexer Control for LD Pin

These bits set the output mode of the LD pin. The table below lists several different modes.

PLL_MUX[3:0]

Output Type

LD Pin Function

0

Hi-Z

Disabled (default)

1

Push-Pull

Logic High

2

Push-Pull

Logic Low

3

Push-Pull

Digital Lock Detect (Active High)

4

Push-Pull

Digital Lock Detect (Active Low)

5

Push-Pull

Analog Lock Detect

6

Open Drain NMOS

Analog Lock Detect

7

Open Drain PMOS

Analog Lock Detect

8

Invalid

9

Push-Pull

N Divider Output/2 (50% Duty Cycle)

10

Invalid

11

Push-Pull

R Divider Output/2 (50% Duty Cycle)

12 to 15

Invalid

"Logic High" and "Logic Low" allow the PLL_MUX pin to be used as a general purpose output. These modes are

also useful when debugging to verify programming. The Digital Lock Detect operation is covered in DIGITAL

LOCK DETECT.

Analog Lock Detect outputs the state of the charge pump on the LD pin. While the charge pump is on, the LD pin

is low. While the charge pump is off, the LD pin is high. By using two resistors, a capacitor, diode, and

comparator a lock detect circuit may be constructed. When in lock the charge pump will only turn on momentarily

once every period of the phase detector frequency. "N Divider Output/2" and "R Divider Output/2" output half the

frequency of the phase detector on the LD pin. When the device is locked, these frequencies should be the

same. These options are useful for debugging.

NOTE

For more information on lock detect circuits, see chapter 32 of PLL Performance,

Simulation and Design Handbook, Fourth Edition by Dean Banerjee.

POWERDOWN bit – Device Power Down

This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of

the state of any of the other bits or pins.

POWERDOWN bit

Mode

0

Normal Operation (default)

1

Entire Device Powered Down

EN_CLKout_Global bit – Global Clock Output Enable

This bit overrides the individual CLKoutX_EN bits (see CLKoutX_EN bit – Clock Output Enables). When this bit is

set to 0, all clock outputs are disabled, regardless of the state of any of the other bits or pins. See CLKout

OUTPUT STATES for more information on CLKout states.

EN_CLKout_Global bit

Clock Outputs

0

All Off

1

Normal Operation (default)

Copyright © 2007–2013, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Links: LMK03002