SDA

SCL

1

8

2

3

7

6

5

8

10

4

9

1

7

ack from slave

start

msb Chip Address lsb

SCL

ack from slave

w

msb Register Add lsb

rs

r

msb

DATA

lsb

stop

ack from slave

ack from master

repeated start

data from slave

SDA

start

id = 59H = 101 1001b

w ack

addr = 00H

ack

rs

r ack

address 00H data

ack stop

msb Chip Address lsb

id = 59H = 101 1001b

start

msb Chip Address lsb

w

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

ack from slave

ack from slave

SCL

SDA

start

id = 59H = 101 1001b

w

ack

addr = 02H

ack

ack

address 02H data

stop

LP3958

SNVS423C – JANUARY 2006 – REVISED MARCH 2013

www.ti.com

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 7-bit chip address, 59H (101 1001b) for LP3958.

Figure 25. I2C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

Figure 26. I2C Read Cycle

Figure 27. I2C Timing Diagram

I2C TIMING PARAMETERS (VDD1,2 = 3.0 to 4.5V, VDDIO = 1.8V to VDD1,2)

Limit(1)

Symbol

Parameter

Unit

Min

Max

1

Hold Time (repeated) START Condition

0.6

µs

(1)

Data guaranteed by design

22

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